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LTC2850IDD8 Datasheet(PDF) 11 Page - Linear Technology

Part # LTC2850IDD8
Description  3.3V 20Mbps RS485/RS422 Transceivers
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC2850IDD8 Datasheet(HTML) 11 Page - Linear Technology

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LTC2850/LTC2851/LTC2852
11
285012fc
APPLICATIONS INFORMATION
Receiver Input Resistance
The receiver input resistance from A or B to ground is
guaranteed to be greater than 96k (C, I-Grade). This is 8x
higher than the requirements for the RS485 standard and
thus this receiver represents a one-eighth unit load. This,
in turn, means that 8x the standard number of receivers,
or 256 total, can be connected to a line without loading
it beyond what is specified in the RS485 standard. The
receiver input resistance from A or B to ground on high
temperature H-Grade parts is greater than 48k providing
a one-quarter unit load. The high input resistance of the
receiver is maintained whether it is enabled or disabled,
powered or unpowered.
Supply Current
The unloaded static supply currents in these devices are
very low, typically under 500μA for all modes of opera-
tion. In applications with resistively terminated cables,
the supply current is dominated by the driver load. For
example, when using two 120
Ω terminators with a dif-
ferential driver output voltage of 2V, the DC load current
is 33mA, which is sourced by the positive voltage supply.
Power supply current increases with toggling data due to
capacitive loading and this term can increase significantly
at high data rates. Figure 13 shows supply current vs
data rate for two different capacitive loads for the circuit
configuration of Figure 4.
High Speed Considerations
A ground plane layout is recommended. A 0.1μF bypass
capacitor less than one-quarter inch away from the VCC pin
is also recommended. The PC board traces connected to
signals A/B and Z/Y should be symmetrical and as short
as possible to maintain good differential signal integrity.
To minimize capacitive effects, the differential signals
should be separated by more than the width of a trace
and should not be routed on top of each other if they are
on different signal planes.
Care should be taken to route outputs away from any
sensitive inputs to reduce feedback effects that might
cause noise, jitter, or even oscillations. For example, in
the full-duplex devices, DI and A/B should not be routed
near the driver or receiver outputs.
The logic inputs have 150mV of hysteresis to provide noise
immunity. Fast edges on the outputs can cause glitches in
the ground and power supplies which are exacerbated by
capacitive loading. If a logic input is held near its threshold
(typically 1.5V), a noise glitch from a driver transition may
exceed the hysteresis levels on the logic and data input
pins causing an unintended state change. This can be
avoided by maintaining normal logic levels on the pins
and by slewing inputs through their thresholds by faster
than 1V/μs when transitioning. Good supply decoupling
and proper driver termination also reduce glitches caused
by driver transitions.
Cable Length vs Data Rate
For a given data rate, the maximum transmission distance
is bounded by the cable properties. A curve of cable length
vs data rate compliant with the RS485/RS422 standards
is shown in Figure 14. Three regions of this curve reflect
different performance limiting factors in data transmis-
sion. In the flat region of the curve, maximum distance
Figure 13. Supply Current vs Data Rate
DATA RATE (Mbps)
0.1
20
60
70
80
1
10
100
285012 F13
50
40
30
RDIFF = 54Ω
CL = 1000pF
CL = 100pF


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