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LTC2915CDDB-1-PBF Datasheet(PDF) 8 Page - Linear Technology |
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LTC2915CDDB-1-PBF Datasheet(HTML) 8 Page - Linear Technology |
8 / 12 page LTC2915/LTC2916 8 29156fa APPLICATIONS INFORMATION Any power supply has some tolerance band within which it is expected to operate (e.g. 5V±10%). It is generally undesirable that a supervisor issue a reset when the power supply is inside this tolerance band. Such a “nuisance” reset reduces reliability by preventing the system from functioning under normal conditions. To prevent nuisance resets, the supervisor threshold must be guaranteed to lie outside the power supply tolerance band. To ensure that the threshold lies outside the power supply tolerance range, the nominal threshold must lie out- side that range by the monitor’s accuracy specification. All 27 of the selectable thresholds have the same relative threshold accuracy of ±1.5% of the programmed nominal input voltage (over the full operating temperature range). Consider the example of monitoring a 5V supply with a 10% tolerance. The nominal threshold internal to the LTC2915 is 11.5% below the 5V input at 4.425V. With ±1.5% ac- curacy, the trip threshold range is 4.425V±75mV over temperature (i.e. 10% to 13% below 5.0V). The monitored system must thus operate reliably down to 4.35V or 13% below 5.0V over temperature. Glitch Immunity The above discussion is concerned only with the DC value of the monitored supply. Real supplies also have relatively high-frequency variation, from sources such as load transients, noise, and pickup. These variations should not be considered by the monitor in determining whether a supply voltage is valid or not. The variations may cause spurious outputs at RST, particularly if the supply voltage is near its trip threshold. Two techniques are used to combat spurious reset without sacrificing threshold accuracy. First, the timeout period helps prevent high-frequency variation whose frequency is above 1/ tRST from appearing at the RST output. When the voltage at VM goes below the threshold, the RST pin asserts low. When the supply recovers past the threshold, the reset timer starts (assuming it is not disabled), and RST does not go high until it finishes. If the supply becomes invalid any time during the timeout period, the timer resets and begins again when the supply next becomes valid. While the reset timeout is useful at preventing toggling of the reset output in most cases, it is not effective at preventing nuisance resets due to short glitches (due to load transients or other effects) on a valid supply. To reduce sensitivity to these short glitches, the comparator has additional anti-glitch circuitry. Any transient at the input of the comparator needs to be of sufficient magnitude and duration tUV before it can change the monitor state. The combination of the reset timeout and anti-glitch cir- cuitry prevents spurious changes in output state without sacrificing threshold accuracy. Adjustable Input When the monitor threshold is configured as ADJ, the internal comparator input is connected to the pin without a resistive divider, and the pin is high-impedance. Thus, any desired threshold may be chosen by attaching VM to a tap point on an external resistive divider between the monitored supply and ground, as shown in Figure 1. The reference input of the comparator is controlled by the tolerance pin. The external resistive divider should make the voltage at VM = 0.5V when the supply is at nominal value. The actual threshold of VM accounts for the sup- ply tolerance of ±1.5% guaranteed over the full operating temperature range. The resulting tolerances are –6.5%, –11.5%, –16.5% which correspond to 0.468V, 0.443V, 0.418V repectively. Figure 1. Setting the Trip Point Using the Adjustable Threshold + – 0.5V VM R2 R1 29156 F01 VMON |
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