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LTC2912IDDB-2 Datasheet(PDF) 10 Page - Linear Technology |
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LTC2912IDDB-2 Datasheet(HTML) 10 Page - Linear Technology |
10 / 12 page LTC2912 10 2912fa TYPICAL APPLICATIONS APPLICATIONS INFORMATION The rise time on the UV, OV and 0V pins is limited by a 400k pull-up resistance to VCC. A similar formula esti- mates the output rise time (10% to 90%) at the UV, OV and OV pins: tRISE ≈ 2.2 • RPU • CLOAD where RPU is the pull-up resistance. OV/OV Latch (LTC2912-1, LTC2912-3) With the LATCH pin held low, the OV pin latches low (LTC2912-1) and the OV pin latches high (LTC2912-3) when an OV condition is detected. The latch is cleared by raising the LATCH pin high. If an OV condition clears while LATCH is held high, the latch is bypassed and the OV and OV pins behave the same as the UV pin with a similar timeout period at the output. If LATCH is pulled low while the timeout period is active, the OV and OV pins latch as before. Disable (LTC2912-2) The LTC2912-2 allows disabling the UV and OV outputs via the DIS pin. Pulling DIS high forces both outputs to remain weakly pulled high, regardless of any faults that occur on the inputs. However, if a UVLO condition oc- curs, UV asserts and pulls low, but the timeout function is bypassed. UV pulls high as soon as the UVLO condition is cleared. DIS has a weak 2μA (typical) internal pull-down current guaranteeing normal operation with the pin left open. Dual UV/OV Supply Monitor, 3.3V ±10% Tolerance 48V Supply Monitor (<±10% = Powergood) Dual UV Supply Monitor, 3.3V, 2.5V, 10% Tolerance RB 1k RC 27.4k VH 1 6 7 2 3 8 4 5 VL GND TMR SYSTEM POWER SUPPLY OV UV 2912 TA02 LATCH CTMR 22nF TIMEOUT = 200ms RA 4.53k VCC LTC2912-1 CBYP 0.1μF 3.3V RB 80.6k RC 37.4M RZ 200k RPG 30k POWERGOOD LED VH 1 6 7 2 3 8 4 5 VL GND TMR POWER SUPPLY OV UV 2912 TA03 DIS RA 357k CTMR 10nF TIMEOUT = 85ms VCC LTC2912-2 CBYP 0.1μF 48V RA1 11k RB1 54.9k RB2 39.2k ROV 10k VH 1 6 7 2 3 8 4 5 VL GND TMR SYSTEM POWER SUPPLIES OV UV 2912 TA04 DIS RA2 11k VCC LTC2912-2 CBYP 0.1μF 2.5V 3.3V RUV 10k |
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