 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
LTC2926CGN Datasheet(PDF) 10 Page - Linear Technology |
|
||||||||||||||||||||||||||||||
LTC2926CGN Datasheet(HTML) 10 Page - Linear Technology |
|
|
10 / 28 page  LTC2926 10 2926fa Power Supply Tracking and Sequencing The LTC2926 handles a variety of power-up profiles to satisfy the requirements of digital logic circuits including FPGAs, PLDs, DSPs and microprocessors. These require- ments fall into one of the four general categories illustrated in Figures 1 to 4. Some applications require that the potential difference between two power supplies must never exceed a speci- fied voltage. This requirement applies during power-up and power-down as well as during steady-state operation, often to prevent destructive latch-up in a dual supply IC. Typically, this is achieved by ramping the supplies up and down together (Figure 1). In other applications it is desirable to have the supplies ramp up and down ratio- metrically (Figure 2) or with fixed voltage offsets between them (Figure 3). Certain applications require one supply to come up after another. For example, a system clock may need to start before a block of logic. In this case, the supplies are se- quenced as in Figure 4, where the 1.8V supply ramps up completely followed by the 2.5V supply. Operation The LTC2926 provides a simple solution to allow all of the power supply tracking and sequencing profiles shown in Figures 1 to 4. A single LTC2926 controls up to three supplies: two “slave” supplies that track a “master” signal. With just four resistors and an external N-channel MOSFET, each slave supply is configured to ramp up and down as a function of the master signal. This master signal can be a third supply that is ramped up through an external MOSFET, whose ramp rate is set with a single capacitor, or it can be a signal generated by tying the MGATE and RAMP pins together to an external capacitor. Tracking Cell and Gate Controller Cell The LTC2926’s operation is based on the combination of a tracking cell and a gate controller cell that is shown in Figure 5. The tracking cell servos the TRACK pin at 0.8V, and the current supplied by the TRACK pin is mirrored at the FB pin. The gate controller cell servos the FB pin at 0.8V by driving the gate of the external N-channel MOSFET (QEXT), and establishes the slave output voltage at the source of the MOSFET based on the TRACK pin current and resistors Figure 4. Supply Sequencing Figure 3. Offset Tracking Figure 2. Ratiometric Tracking Figure 1. Coincident Tracking APPLICATIO S I FOR ATIO 2926 F01 500mV/DIV MASTER SLAVE2 SLAVE1 5ms/DIV 2926 F02 500mV/DIV SLAVE2 SLAVE1 5ms/DIV 2926 F04 500mV/DIV SLAVE2 SLAVE1 5ms/DIV 2926 F03 500mV/DIV MASTER SLAVE2 SLAVE1 5ms/DIV |
Similar Part No. - LTC2926CGN |
|
Similar Description - LTC2926CGN |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
