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LTC2930HDD-PBF Datasheet(PDF) 6 Page - Linear Technology |
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LTC2930HDD-PBF Datasheet(HTML) 6 Page - Linear Technology |
6 / 12 page LTC2930 6 2930fa PIN FUNCTIONS A/D BUFFER 1.210V 8 VPG 3 V1 11 V2 2 V3 10 V4 1 V5 12 V6 9 VREF 4 0.5V 4 2931 BD BANDGAP REFERENCE ADJUSTABLE RESET PULSE GENERATOR POWER DETECT V1 V2 VCC 4 CRT 6 MR CRT VCC VCC 22μA RESISTIVE DIVIDER MATRIX 4 – + 7 GND V2 6μA 2μA 5 RST CMP1-4 CMP5 CMP6 10μA MR (Pin 6): Manual Reset Input. A logic low on this pin pulls RST low. When the MR pin returns high, RST returns high after the configured reset timeout if all six voltage inputs are above threshold. A weak internal pull-up allows the pin to be left open for normal monitor operation. When using a switch, the switch is debounced through the reset circuitry using the delay provided by the CRT timing capacitor. GND (Pin 7): Ground. VPG (Pin 8): Threshold Select Input. Connect to an external 1% resistive divider between VREF and GND to select 1 of 16 combinations and/or ±adjustable voltage thresholds (See Table 1). Do not add capacitance on the VPG pin. VREF (Pin 9): Buffered Reference Voltage Output. A 1.210V nominal reference used for the mode selection voltage (VPG) and for the offset of negative adjustable applications. The buffered reference can source and sink up to 1mA. The reference can drive a bypass capacitor of up to 1000pF without oscillation. V4 (Pin 10): Voltage Input 4. Select from 1.8V, 1.5V, ADJ or –ADJ. See Applications Information for details. Tie to V1 if unused. V2 (Pin 11): Voltage Input 2. Select from 3.3V, 3V or 2.5V. See Applications Information for details. The greater of V1, V2 is also VCC for the device. Bypass this pin to ground with a 0.1μF (or greater) capacitor. RST is weakly pulled up to V2. V6 (Pin 12): Adjustable Voltage Input 6. High impedance comparator input with 0.5V typical threshold. See Applications Information for details. Tie to V1 if unused. Exposed Pad (Pin 13): Exposed pad may be left open or connected to device ground. BLOCK DIAGRAM |
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