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LTC3220EPF-TRPBF Datasheet(PDF) 11 Page - Linear Technology |
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LTC3220EPF-TRPBF Datasheet(HTML) 11 Page - Linear Technology |
11 / 20 page LTC3220/LTC3220-1 11 32201fb Figure 3. Timing Parameters ACK 123 ADDRESS WR 456789 12345678 9 123456789 0 0 11 1 000 0 0 111010 S7 S6 S5 S4 S3 S2 S1 S0 76543210 ACK STOP START SDA SCL ACK ADDRESS LTC3220-1 LTC3220 WR 0 0 111000 S7 S6 S5 S4 S3 S2 S1 S0 76543210 SUB-ADDRESS DATA BYTE 3220 FO2 Figure 2. Bit Assignments tSU, DAT t HD, STA tHD, DAT SDA SCL tSU, STA tHD, STA tSU, STO 3220 F03 tBUF tLOW tHIGH START CONDITION REPEATED START CONDITION STOP CONDITION START CONDITION tr tf tSP sub-address register is then written to, followed by the data register. Each data register has a sub-address. After the data register has been written a load pulse is created after the stop bit. The load pulse transfers all of the data held in the data registers to the DAC registers. The stop bit can be delayed until all of the data master registers have been written. At this point the LED current will be changed to the new settings. The serial port uses static logic registers so there is no minimum speed at which it can be operated. I2C Interface The LTC3220/LTC3220-1 communicate with a host (master) using the standard I2C 2-wire interface. The Timing Diagram (Figure 3) shows the timing relationship of the signals on the bus. The two bus lines, SDA and SCL, must be high when the bus is not in use. External pull-up resistors or current sources, such as the LTC1694 SMBus accelerator, are required on these lines. The LTC3220/LTC3220-1 are receive-only (slave) devices. There are two I2C addresses available. The LTC3220 I2C address is 0011100 and the LTC3220-1 I2C address is 0011101. The I2C address is the only difference between the LTC3220 and LTC3220-1. Write Word Protocol Used By the LTC3220/LTC3220-1 17 1 1 8 1 8 1 1 S Slave Address Wr A *Sub-Address A Data Byte A P** S = Start Condition, Wr = Write Bit = 0, A = Acknowledge, P = Stop Condition *The sub-address uses only the first 5 bits, D0, D1, D2, D3 and D4. **Stop can be delayed until all of the data registers have been written. OPERATION |
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