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LTC3561 Datasheet(PDF) 9 Page - Linear Technology |
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LTC3561 Datasheet(HTML) 9 Page - Linear Technology |
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9 / 16 page  LTC3561 9 3561f reduces surge currents from VIN by gradually increasing the peak inductor current. Power supply sequencing can also be accomplished using this pin. The LTC3561 has an internal digital soft-start which steps up a clamp on ITH over 1024 clock cycles, as can be seen in Figure 3. The soft-start time can be increased by ramping the voltage on ITH during start-up as shown in Figure 2(c). As the voltage on ITH ramps through its operating range the internal peak current limit is also ramped at a proportional linear rate. Checking Transient Response The OPTI-LOOP compensation allows the transient re- sponse to be optimized for a wide range of loads and output capacitors. The availability of the ITH pin not only allows optimization of the control loop behavior but also provides a DC coupled and AC filtered closed loop re- sponse test point. The DC step, rise time and settling at this test point truly reflects the closed loop response. Assum- ing a predominantly second order system, phase margin and/or damping factor can be estimated using the percent- age of overshoot seen at this pin. The bandwidth can also be estimated by examining the rise time at the pin. The ITH external components shown in the front page circuit will provide an adequate starting point for most applications. The series R-C filter sets the dominant pole- zero loop compensation. The values can be modified slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the final PC layout is done and the particular output capacitor type and value have been determined. The output capacitors need to be selected because the various types and values determine the loop feedback factor gain and phase. An output current pulse of 20% to 100% of full load current having a rise time of 1 µs to 10µs will produce output voltage and ITH pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to ∆ILOAD • ESR, where ESR is the effective series resistance of COUT. ∆ILOAD also begins to charge or discharge COUT generat- ing a feedback error signal used by the regulator to return VOUT to its steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem. The initial output voltage step may not be within the bandwidth of the feedback loop, so the standard second order overshoot/DC ratio cannot be used to determine phase margin. The gain of the loop increases with R and the bandwidth of the loop increases with decreasing C. If R is increased by the same factor that C is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. In addition, a feedforward capacitor CF can be added to improve the high frequency response, as shown in Figure 5. Capacitor CF provides phase lead by creating a high frequency zero with R2 which improves the phase margin. APPLICATIO S I FOR ATIO Figure 3. Digital Soft-Start Figure 2. SHDN/RT Pin Interfacing and External Soft-Start 3561 F03a RUN RT SHDN/RT 3561 F03b RUN RT SHDN/RT 1M SVIN 3561 F03c RUN OR VIN ITH C1 CC D1 RC R1 (2c) (2b) (2a) VIN 2V/DIV VOUT 2V/DIV IL 500mA/DIV 200 µs/DIV 3411 F04.eps VIN = 3.3V VOUT = 2.5V RL = 1.4Ω |
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