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LTC3525-3.3 Datasheet(PDF) 7 Page - Linear Technology |
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LTC3525-3.3 Datasheet(HTML) 7 Page - Linear Technology |
7 / 12 page LTC3525-3/ LTC3525-3.3/LTC3525-5 7 3525fa BLOCK DIAGRA PI FU CTIO S ⎯S⎯H⎯D⎯N (Pin 1): Logic Controlled Shutdown Input. Con- nect to a voltage >1V to enable the LTC3525. Connect to a voltage <0.4V to disable the LTC3525. GND (Pins 2, 5): Ground. VIN (Pin 3): Input Voltage. The LTC3525 is powered from VIN until VOUT exceeds VIN. Once VOUT is greater than (VIN + 0.2V typical), it is powered from VOUT. Place a ceramic bypass capacitor from VIN to GND. A minimum value of 1µF is recommended. VOUT (Pin 4): Output Voltage Sense and the Output of the Synchronous Rectifier. Connect the output filter capacitor from VOUT to GND, close to the IC. A minimum value of 10µF ceramic is recommended. Use 22µF for reduced output ripple. The output disconnect feature disconnects VOUT from VIN when ⎯S⎯H⎯D⎯N is <0.4V. SW (Pin 6): Switch Pin. Connect an inductor from this pin to VIN. An internal antiringing resistor is connected across SW and VIN after the inductor current has dropped to zero to minimize EMI. + – + – 3 6 1 2 4 VREF IPK COMPARATOR IVALLEY COMPARATOR SLEEP COMPARATOR INTEGRATOR WAKE TSD IVAL VOUT VIN SHDN SW IPK ADJUST GND 5 GND FB OFFSET ADJUST OFFSET ADJUST LOGIC GATE DRIVERS AND ANTI-CROSS CONDUCTION WELL SWITCH VBEST VREF UVLO THERMAL SHUTDOWN VB SHUTDOWN STARTUP UVLO SHUTDOWN SHUTDOWN VREF VSEL VOUT 3525 BD |
Similar Part No. - LTC3525-3.3 |
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Similar Description - LTC3525-3.3 |
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