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LTC3736EGN-2 Datasheet(PDF) 7 Page - Linear Technology |
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LTC3736EGN-2 Datasheet(HTML) 7 Page - Linear Technology |
7 / 28 page 7 LTC3736-2 37362fa FU CTIO AL DIAGRA – + – + SHDN 0.6V VREF EXTSS 0.7 µA CLK1 CLK2 FCB 0.54V VFB1 VFB2 FCB 0.6V SLOPE1 SLOPE2 RUN/SS VIN CVIN VIN (TO CONTROLLER 1, 2) RVIN SYNC/FCB PLLLPF UNDERVOLTAGE LOCKOUT SYNC DETECT VOLTAGE CONTROLLED OSCILLATOR SLOPE COMP VOLTAGE REFERENCE tSEC = 1ms INTSS PHASE DETECTOR PGOOD SHDN OV1 UV1 UV2 OV2 37362 FD (Common Circuitry) resistor divider from the auxiliary output. To synchronize with an external clock using the PLL, apply a CMOS compatible clock with a frequency between 250kHz and 850kHz. To select pulse-skipping operation at light loads, tie this pin to VIN. Grounding this pin selects forced continuous operation, which allows the inductor current to reverse. When synchronized to an external clock, pulse- skipping operation is enabled at light loads. BG1/BG2 (Pins 19, 13/Pins 22, 16): Bottom (NMOS) Gate Drive Output. These pins drive the gates of the external N- channel MOSFETs. These pins have an output swing from PGND to SENSE+. SENSE1+/SENSE2+ (Pins 21, 11/Pins 24, 14): Positive Input to Differential Current Comparator. Also powers the gate drivers. Normally connected to the source of the ex- ternal P-channel MOSFET. SW1/SW2 (Pins 22, 10/Pins 1, 13): Switch Node Connec- tion to Inductor. Also the negative input to differential peak current comparator and an input to the reverse current com- parator. Normally connected to the drain of the external P- channel MOSFETs, the drain of the external N-channel MOSFET, and the inductor. IPRG1/IPRG2 (Pins 23, 2/Pins 2, 5): Three-State Pins to Select Maximum Peak Sense Voltage Threshold. These pins select the maximum allowed voltage drop between the SENSE+ and SW pins (i.e., the maximum allowed drop across the external P-channel MOSFET) for each channel. Tie to VIN, GND or float to select 345mV, 167mV, or 240mV respectively. VFB1/VFB2(Pins24,7/Pins3,10):FeedbackPins.Receives the remotely sensed feedback voltage for its controller from an external resistor divider across the output. PI FU CTIO S |
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