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PE43702MLI-Z Datasheet(PDF) 6 Page - Peregrine Semiconductor Corp. |
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PE43702MLI-Z Datasheet(HTML) 6 Page - Peregrine Semiconductor Corp. |
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6 / 11 page  Product Specification PE43702 Page 6 of 11 ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0244-03 │ UltraCMOS™ RFIC Solutions Programming Options Parallel/Serial Selection Either a parallel or serial interface can be used to control the PE43702. The P/S bit provides this selection, with P/S=LOW selecting the parallel interface and P/S=HIGH selecting the serial interface. Parallel Mode Interface The parallel interface consists of seven CMOS- compatible control lines that select the desired attenuation state, as shown in Table 7. The parallel interface timing requirements are defined by Fig. 16 (Parallel Interface Timing Diagram), Table 11 (Parallel Interface AC Characteristics), and switching speed (Table 1). For latched-parallel programming the Latch Enable (LE) should be held LOW while changing attenuation state control values, then pulse LE HIGH to LOW (per Fig. 16) to latch new attenuation state into device. For direct parallel programming, the Latch Enable (LE) line should be pulled HIGH. Changing attenuation state control values will change device state to new attenuation. Direct Mode is ideal for manual control of the device (using hardwire, switches, or jumpers). Serial Interface The serial interface is a 8-bit serial-in, parallel-out shift register buffered by a transparent latch. The 8-bits make up the Attenuation Word that controls the DSA. Fig. 15 illustrates a example timing diagram for programming a state. The serial-interface is controlled using three CMOS-compatible signals: Serial-In (SI), Clock (CLK), and Latch Enable (LE). The SI and CLK inputs allow data to be serially entered into the shift register. Serial data is clocked in LSB first. The shift register must be loaded while LE is held LOW to prevent the attenuator value from changing as data is entered. The LE input should then be toggled HIGH and brought LOW again, latching the new data into the DSA. Attenuation Word truth table is listed in Table 9. A programming example of the serial register is illustrated in Table 8. The serial timing diagram is illustrated in Fig. 15. It is recommended that all parallel pins be grounded when the DSA is used in serial mode. Power-up Control Settings The PE43702 will always initialize to the maximum attenuation setting (31.75 dB) on power-up for both the serial and latched-parallel modes of operation and will remain in this setting until the user latches in the next programming word. In direct-parallel mode, the DSA can be preset to any state within the 31.75 dB range by pre-setting the parallel control pins prior to power-up. In this mode, there is a 400- µs delay between the time the DSA is powered-up to the time the desired state is set. During this power-up delay, the device attenuates to the maximum attenuation setting (31.75 dB) before defaulting to the user defined state. If the control pins are left floating in this mode during power-up, the device will default to the minimum attenuation setting (insertion loss state). |
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