PE97022-11 datasheet(4/14 Pages) PEREGRINE

Part #	PE97022-11

Description	3500 MHz UltraCMOS Integer-N PLL Rad Hard for Space Applications

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Manufacturer	PEREGRINE [Peregrine Semiconductor Corp.]

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4 / 14 page

Product Specification

PE97022

Page 4 of 14

Document No. 70-0235-04

│ UltraCMOS™ RFIC Solutions

Table 1. Pin Descriptions (continued)

Note 1:

VDD pins 1, 11, 12, 23, 31, 33, 35, and 38 are connected by diodes and must be supplied with the same positive voltage level.

VDD pins 31 and 38 are used to enable test modes and should be left floating.

Note 2:

All digital input pins have 70 k

Ω pull-down resistors to ground.

Pin No.

Pin Name

Interface Mode

Type

Description

31

VDD-fp

ALL

(Note 1)

VDD for fp. Can be left floating or connected to GND to disable the fp output.

32

Dout

Serial, Parallel

Output

Data Out. The MSEL signal and the raw prescaler output are available on Dout

through enhancement register programming.

33

VDD

ALL

(Note 1)

Same as pin 1.

34

Cext

ALL

Output

Logical “NAND” of PD_

Ū and PD_D

¯ terminated through an on chip, 2 kΩ series

resistor. Connecting Cext to an external capacitor will low pass filter the input to the

inverting amplifier used for driving LD.

35

VDD

ALL

(Note 1)

Same as pin 1.

36

PD_D

¯

ALL

Output

PD_D

¯ is pulse down when f

p leads fc.

37

PD_

Ū

ALL

PD_

Ū is pulse down when f

c leads fp.

38

VDD-fc

ALL

(Note 1)

VDD for fc. Can be left floating or connected to GND to disable the fc output.

39

fc

ALL

Output

Monitor pin for reference divider output. Switching activity can be disabled through

enhancement register programming or by floating or grounding VDD pin 38.

40

GND

ALL

Ground.

41

GND

ALL

Ground.

42

fr

ALL

Input

Reference frequency input.

43

LD

ALL

Output,

OD

Lock detect and open drain logical inversion of CEXT. When the loop is in lock, LD

is high impedance, otherwise LD is a logic low (“0”).

44

E

¯n¯h¯

Serial, Parallel

Input

Enhancement mode. When asserted low (“0”), enhancement register bits are

functional.

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