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LTC3853EUJ-TRPBF Datasheet(PDF) 9 Page - Linear Technology |
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LTC3853EUJ-TRPBF Datasheet(HTML) 9 Page - Linear Technology |
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9 / 36 page  LTC3853 9 3853f TG1, TG2, TG3 (Pins 32, 26, 19): Top Gate Driver Outputs. These are the outputs of floating drivers with a voltage swing equal to INTVCC superimposed on the switch nodes voltages. BOOST1, BOOST2, BOOST3 (Pins 33, 25, 18): Boosted Floating Driver Supplies. The (+) terminal of the booststrap capacitors connect to these pins. These pins swing from a diode voltage drop below INTVCC up to VIN + INTVCC. RUN1, RUN2, RUN3 (Pins 36, 35, 34): Run Control In- puts. A voltage above 1.2V on any RUN pin turns on the IC. However, forcing any of these pins below 1.2V causes the IC to shut down the circuitry required for that particular channel. There are 0.5μA pull-up currents for these pins. Once the RUN pin rises above 1.2V, an additional 4.5μA pull-up current is added to the pin. MODE/PLLIN (Pin 37): Force Continuous Mode, Burst Mode, or Pulse Skip Mode Selection Pin and External Synchronization Input to Phase Detector Pin. Connect this pin to SGND to force all channels into the continuous mode of operation. Connect to INTVCC to enable pulse skip mode of operation. Leaving the pin floating will en- able Burst Mode operation. A clock on the pin will force the controller into continuous mode of operation and synchronize the internal oscillator. FREQ/PLLFLTR (Pin 38): The phase-locked loop’s low- pass filter is tied to this pin. Alternatively, this pin can be driven with a DC voltage to vary the frequency of the internal oscillator. ILIM (Pin 39): Current Comparator Sense Voltage Range Inputs. This pin is to be programmed to SGND, FLOAT or INTVCC to set the maximum current sense threshold to three different levels. TK/SS1, TK/SS2, TK/SS3 (Pins 40, 1, 2): Output Voltage Tracking and Soft-Start Inputs. When one particular channel is configured to be the master, a capacitor to ground at this pin sets the ramp rate for the master channel’s output voltage. When the channel is configured to be the slave, the VFB voltage of the master channel is reproduced by a resistor divider and applied to this pin. Internal soft-start currents of 1.3μA are charging the soft-start capacitors. In dual output (2 + 1) mode, TK/SS1 and TK/SS2 need to be shorted externally. Exposed Pad (Pin 41): Power Ground. Connect these pins closely to the sources of the bottom N-channel MOSFETs, the (–) terminal of CVCC and the (–) terminal of CIN. PIN FUNCTIONS |
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