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FD7799T-25.0M-PLE-1K Datasheet(PDF) 11 Page - Pletronics, Inc. |
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FD7799T-25.0M-PLE-1K Datasheet(HTML) 11 Page - Pletronics, Inc. |
11 / 19 page FD7T Series Multi-Output CMOS Clock Oscillator May 2008 www.pletronics.com 425-776-1880 11 0 5 10 15 20 25 30 10 30 50 70 90 110 130 150 170 190 210 230 Fout (MHz) 0 2 4 6 8 10 12 14 10 30 50 70 90 110 130 150 170 190 210 230 Fout (MHz) 7 Outputs On 6 Outputs On 5 Outputs On 4 Outputs On 3 Outputs On 2 Outputs On 1 Output On All outputs Off 0 1 2 3 4 5 6 7 8 9 10 10 30 50 70 90 110 130 150 170 190 210 230 Fout (MHz) 7 Outputs On 6 Outputs On 5 Outputs On 4 Outputs On 3 Outputs On 2 Outputs On 1 Output On All outputs Off 0 2 4 6 8 10 12 14 16 18 20 10 30 50 70 90 110 130 150 170 190 210 230 Fout (MHz) 0 10 20 30 40 50 60 70 80 90 10 30 50 70 90 110 130 150 170 190 210 230 PLL Frequency (MHz) 4 PLLs On 3 PLLs On 2 PLLs On 1 PLL On All PLLs Off FD7xxxT I DDOUT Current for Various Number of Outputs On No Load VDD=1.8V V DDOUT=3.3V V DDOUT=2.5V V DDOUT=1.8V FD7xxxTL V DD = VDDOUT=1.8V FD7 Series I DD versus PLLs Used No Load V DD=1.8V Phase noise of the reference signal, Out1. 25MHz Reference Frequency RMS jitter is 1.4pS from 10Hz to 2MHz Example of the PLL synthesizing a frequency. 25MHz Reference Frequency Multiply by 8 to 200MHz Divide the 200MHz PLL output by 8 Phase noise plot of the resulting 25MHz on Out 2 |
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