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L9D125G80BG4M6 Datasheet(PDF) 11 Page - LOGIC Devices Incorporated |
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L9D125G80BG4M6 Datasheet(HTML) 11 Page - LOGIC Devices Incorporated |
11 / 45 page LOGIC Devices Incorporated www.logicdevices.com Feb 2, 2009 LDS-L9D125G80BG4-C 11 2.5 Gb, DDR - SDRAM Integrated Module (IMOD) PreLIMINArY INforMAtIoN L9D125G80BG4 High Performance, Integrated Memory Module Product REGISTER DEFINITION Figure 3 - extenDeD moDe register Notes: 1. n is the most significant row address bit. . 2. The reduced drive strength option is available only on Design Revision F and K. 3. The QFC# option is not supported. Operating Mode Reserved Reserved E3 0 – E4 0 – E1, E0 Valid – DLL Enable Disable A9 A7 A6 A5 A4 A3 A8 A2 A1 A0 Extended mode register (Ex) Address bus 9 7 6 5 4 3 8 2 1 0 1 E0 0 1 Drive Strength Normal Reduced E12 Operating Mode . . . An BA1 BA0 . . . n1 n + 1 n + 2 E6 0 – E7 0 – E8 0 – E9 0 – E5 0 – . . . 0 – En 0 – DS E23 0 – Mn + 1 0 1 0 1 Mode Register Definition Base mode register Extended mode register Reserved Reserved Mn + 2 0 0 1 1 DLL 0 1 0 The normal full drive strength for all outputs are specified to be SSTL2, Class II. The DDR IMOD supports an option for reduced drive. This option is intended for the support of the lighter load and/or point-to-point environ- ments. The selection of the reduced drive strength will alter the DQs and DQSs from SSTL2, Class II drive strength to a reduced drive strength, which is approximately 54% of the SSTL, Class II drive strength. The DLL must be enabled for normal operation. The DLL enable is required during power-up initialization and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. When the device exits SELF REFRESH mode, the DLL is enabled, 200 clock cycles must occur before a READ command can be issued. outPut Drive strength Dll enaBle/DisaBle |
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