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MX25L3205DZNI-12G Datasheet(PDF) 3 Page - Macronix International |
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MX25L3205DZNI-12G Datasheet(HTML) 3 Page - Macronix International |
3 / 56 page 3 MX25L1605D MX25L3205D MX25L6405D P/N: PM1290 REV. 1.4, OCT. 01, 2008 Table 1. Additional Feature Comparison To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit. Advanced security features enhance the protection and security functions, please see security features section for more details. When the device is not in operation and CS# is high, it is put in standby mode and draws less than 20uA DC current. The MX25L1605D/3205D/6405D utilizes MXIC's proprietary memory cell, which reliably stores memory contents even after typical 100,000 program and erase cycles. Read Performance MX25L1605D V V V 14 (hex) C2 14 (hex) (if ADD=0) C2 14 (hex) (if ADD=0) C2 20 15 (hex) Identifier Protection and Security Featu- res Part Name Additional Device ID (command : EF hex) RDID (command: 9F hex) 512-bit secured OTP 2 I/O Read (50MHz) Device ID (command : AB hex) Device ID (command : 90 hex) Flexible Block protection (BP0-BP3) MX25L3205D V V V 15 (hex) C2 15 (hex) (if ADD=0) C2 15 (hex) (if ADD=0) C2 20 16 (hex) MX25L6405D V V V 16 (hex) C2 16 (hex) (if ADD=0) C2 16 (hex) (if ADD=0) C2 20 17 (hex) |
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