MX29LV128DTTI-90Q datasheet(6/73 Pages) MCNIX

Part #	MX29LV128DTTI-90Q

Description	128M-BIT [16M x 8/8M x 16] SINGLE VOLTAGE 3V ONLY FLASH MEMORY

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Manufacturer	MCNIX [Macronix International]

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P/N:PM1327

REV. 1.0, SEP. 22, 2008

MX29LV128D T/B

BLOCK DIAGRAM DESCRIPTION

The block diagram on Page 4 illustrates a simplified architecture of MX29LV128D T/B. Each block in the block diagram

represents one or more circuit modules in the real chip used to access, erase, program, and read the memory array.

The "CONTROL INPUT LOGIC" block receives input pins CE#, OE#, WE#, RESET#, BYTE#, and WP#/ACC. It

creates internal timing control signals according to the input pins and outputs to the "ADDRESS LATCH AND BUFFER"

to latch the external address pins A0-AM(A22).The internal addresses are output from this block to the main array and

decoders composed of "X-DECODER", "Y-DECODER", "Y-PASS GATE", AND "FLASH ARRAY". The X-DECODER

decodes the word-lines of the flash array, while the Y-DECODER decodes the bit-lines of the flash array. The bit lines

are electrically connected to the "SENSE AMPLIFIER" and "PGM DATA HV" selectively through the Y-PASS GATES.

SENSE AMPLIFIERS are used to read out the contents of the flash memory, while the "PGM DATA HV" block is used

to selectively deliver high power to bit-lines during programming. The "I/O BUFFER" controls the input and output on

the Q0-Q15/A-1 pads. During read operation, the I/O BUFFER receives data from SENSE AMPLIFIERS and drives

the output pads accordingly. In the last cycle of program command, the I/O BUFFER transmits the data on Q0-Q15/A-

1 to "PROGRAM DATA LATCH", which controls the high power drivers in "PGM DATA HV" to selectively program the

bits in a word or byte according to the user input pattern.

The "PROGRAM/ERASE HIGH VOLTAGE" block comprises the circuits to generate and deliver the necessary high

voltage to the X-DECODER, FLASH ARRAY, and "PGM DATA HV" blocks. The logic control module comprises of the

"WRITE STATE MACHINE, WSM", "STATE REGISTER", "COMMAND DATA DECODER", and "COMMAND DATA

LATCH". When the user issues a command by toggling WE#, the command on Q0-A15/A-1 is latched in the COM-

MAND DATA LATCH and is decoded by the COMMAND DATA DECODER. The STATE REGISTER receives the

command and records the current state of the device. The WSM implements the internal algorithms for program or

erase according to the current command state by controlling each block in the block diagram.

ARRAY ARCHITECTURE

The main flash memory array can be organized as 16M Bytes x 8 or as 8M Words x 16. The details of the address

ranges and the corresponding sector addresses are shown in Table 1.Table 1.a shows the sector group architecture for

the Top Boot part, whereas Table 1.b shows the sector group architecture for the Bottom Boot part. The specific

security sector addresses are shown at the bottom off each of these tables.

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