Features

ä Power monitoring and switching

for nonvolatile control of SRAMs

ä Write-protect control

ä Battery-low and battery-fail indi-

cators

ä Reset output for system power-on

reset

ä Input decoder for control of up to

2 banks of SRAM

ä 3-volt primary cell input

ä 3-volt rechargeable battery in-

put/output

General Description

The CMOS bq2203A SRAM Nonvolatile

Controller With Battery Monitor pro-

vides all the necessary functions for con-

verting one or two banks of standard

CMOS

SRAM

into

nonvolatile

read/write memory. The bq2203A is

compatible with the Personal Computer

Memory Card International Association

(PCMCIA) recommendations for

battery-backed static RAM memory

cards.

A precision comparator monitors the 5V

tion. When out of tolerance is detected,

the two conditioned chip-enable outputs

are forced inactive to write-protect

banks of SRAM.

Power for the external SRAMs is

cays. On a subsequent power-up, the

switched from the backup supply to

are write-protected until a power-

valid condition exists. The reset out-

put provides power-fail and power-on

resets for the system.

The battery

monitor indicates battery-low and

battery-fail conditions.

During power-valid operation, the

input decoder selects one of two

banks of SRAM.

1

1

PN220301.eps

16-Pin Narrow DIP or SOIC

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

VCC

BCS

CE

CECON1

CECON2

BCL

RST

NC

VOUT

BCP

NC

A

BCF

NC

THS

VSS

bq2203A

Nov. 1994 B

Pin Connections

Two banks of CMOS static RAM can be battery-backed us-

during a power failure, the two conditioned chip-enable

independent of the chip-enable input CE.

This activity unconditionally write-protects external SRAM

selected by the threshold select input pin, THS. If THS is

for 5% supply operation.

4.37V typical for 10% supply operation. The THS pin

If a memory access is in process to any of the two exter-

nal banks of SRAM during power-fail detection, that

memory cycle continues to completion before the memory

is write-protected. If the memory cycle is not terminated

outputs are unconditionally driven high, write-protecting

the controlled SRAMs.

Functional Description

NV Controller With Battery Monitor

Pin Names

Supply output

RST

Reset output

THS

Threshold select input

CE

chip-enable active low input

Conditioned chip-enable outputs

A

Bank select input

BCF

Battery fail push-pull output

BCL

Battery low push-pull output

3V backup supply input

3V rechargeable backup supply input/output

NC

No connect

5-volt supply input

Ground