CDCVF2509

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

SCAS637 – DECEMBER 1999

9

POST OFFICE BOX 655303

TYPICAL CHARACTERISTICS

Figure 7

120

100

80

0

60

40

20

fc – Clock Frequency – MHz

JITTER

vs

CLOCK FREQUENCY AT FBOUT

140

50

75

100

125

150

175

200

VCC = 3.3 V

C(LY) = 25 pF || 500 Ω

C(LF) = 12 pF || 500 Ω

TA = 25°C

See Notes C and D

Cycle to Cycle

Figure 8

ANALOG SUPPLY CURRENT

vs

CLOCK FREQUENCY

25

15

10

5

0

20

0

25

50

75

100

125

150

175

AVCC = VCC = 3.6 V

Bias = 0/3 V

C(LY) = 25 pF || 500 Ω

C(LF) = 12 pF || 500 Ω

TA = 25°C

See Notes A and B

fc – Clock Frequency – MHz

200

SUPPLY CURRENT

vs

CLOCK FREQUENCY

250

150

100

50

0

200

fc – Clock Frequency – MHz

0

25

50

75

100

125

150

175

200

AVCC = VCC = 3.6 V

Bias = 0/3 V

C(LY) = 25 pF || 500 Ω

C(LF) = 12 pF || 500 Ω

TA = 25°C

See Notes A and B

Figure 9

NOTES: A. Trace length FBOUT to FBIN = 5 mm, ZO = 50 Ω

B. Total current = ICC + AICC

C. C(LY) = Lumped capacitive load Y1–n

D. C(LFx) = Lumped feedback capacitance at FBOUT = FBIN