10-Bit Latch

CY54/74FCT841T

SCCS035 - September 1994 - Revised March 2000

Data sheet acquired from Cypress Semiconductor Corporation.

Data sheet modified to remove devices not offered.

Copyright

Features

• Function, pinout, and drive compatible with FCT, F, and

AM29841 logic

• FCT-C speed at 5.5 ns max. (Com’l)

FCT-B speed at 6.5 ns max. (Com’l)

FCT functions

• Edge-rate control circuitry for significantly improved

noise characteristics

• Power-off disable feature

• Matched rise and fall times

• ESD > 2000V

• Fully compatible with TTL input and output logic levels

• Sink current

64 mA (Com’l),

32 mA (Mil)

Source current

32 mA (Com’l),

12 mA (Mil)

• High-speed parallel latches

• Buffered common latch enable input

Functional Description

The FCT841T bus interface latch is designed to eliminate the

extra packages required to buffer existing latches and provide

extra data width for wider address/data paths or buses

carrying parity. The FCT841T is a buffered 10-bit wide version

of the FCT373 function.

The FCT841T high-performance interface is designed for

high-capacitance

load

drive

capability

while

providing

low-capacitance bus loading at both inputs and outputs.

Outputs are designed for low-capacitance bus loading in the

high impedance state and are designed with a power-off

disable feature to allow for live insertion of boards.

Logic Block Diagram

Pin Configurations

D

OE

LE

Q

DQ

Q

DQ

Q

DQ

Q

DQ

Q

DQ

Q

DQ

Q

DQ

Q

LE

LE

LE

LE

LE

LE

LE

D

Y

Q

LE

D

LE

OE

10

10

1

2

3

4

5

6

7

8

9

10

11

12

16

17

18

19

20

24

23

22

21

13

14

15

DIP/QSOP/SOIC

Top View

OE

GND

LE

Functional Block Diagram

LE