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CY74FCT163500TSSOP Datasheet(PDF) 1 Page - Texas Instruments |
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CY74FCT163500TSSOP Datasheet(HTML) 1 Page - Texas Instruments |
1 / 7 page 18-Bit Registered Transceiver CY74FCT163500 SCCS066 - June 1997 - Revised March 2000 Data sheet acquired from Cypress Semiconductor Corporation. Data sheet modified to remove devices not offered. Copyright © 2000, Texas Instruments Incorporated Features • Low power, pin-compatible replacement for LCX and LPT families • 5V tolerant inputs and outputs • 24 mA balanced drive outputs • Power-off disable outputs permits live insertion • Edge-rate control circuitry for reduced noise • FCT-C speed at 4.6 ns • Latch-up performance exceeds JEDEC standard no. 17 • ESD > 2000V per MIL-STD-883D, Method 3015 • Typical output skew < 250ps • Industrial temperature range of –40˚C to +85˚C • TSSOP (19.6-mil pitch) or SSOP (25-mil pitch) • Typical Volp (ground bounce) performance exceeds Mil Std 883D •VCC = 2.7V to 3.6V Functional Description The CY74FCT163500 is an 18-bit universal bus transceiver that can be operated in transparent, latched, or clock modes by combining D-type latches and D-type flip-flops. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock inputs (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the HIGH-to-LOW transition of CLKAB. OEAB performs the output enable function on the B port. Data flow from B-to-A is similar to that of A-to-B and is controlled by OEBA, LEBA, and CLKBA. The CY74FCT163500 has 24-mA balanced output drivers with current limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce.The inputs and outputs are capable of being driven by 5.0V busses, allowing them to be used in mixed voltage systems as translators. The outputs are also designed with a power off disable feature enabling them to be used in applications requiring live insertion. GND Logic Block Diagram Pin Configuration 1 2 3 4 5 6 7 8 9 10 11 12 33 32 31 30 29 36 35 OEAB 34 SSOP/TSSOP Top View 13 14 15 16 17 18 19 20 21 22 23 24 45 44 43 42 41 37 38 39 40 48 47 46 LEAB A1 A2 A3 B1 B2 B3 GND GND GND VCC A6 A7 A4 A5 B4 B5 B6 B7 VCC GND A10 A11 A8 A9 B8 B9 B11 B12 GND A12 VCC A16 GND A14 VCC A15 A17 TO 17 OTHER CHANNELS LEAB OEBA LEBA CLKAB CLKBA OEAB C D C D C D C D A1 B1 25 26 27 28 49 52 51 50 A13 OEBA LEBA GND A18 CLKAB 53 56 55 54 B10 GND B14 B15 B13 B16 B17 GND B18 CLKBA |
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