MSP430P325

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

11

POST OFFICE BOX 655303

LCD drive

Liquid crystal displays (LCDs) for static, 2-, 3- and 4-MUX operations can be driven directly. The controller LCD

logic operation is defined by software using memory-bit manipulation. LCD memory is part of the LCD module,

not part of data memory. Eight mode and control bits define the operation and current consumption of the LCD

drive. The information for the individual digits can be easily obtained using table programming techniques

combined with the correct addressing mode. The segment information is stored in LCD memory using

instructions for memory manipulation.

The drive capability is mainly defined by the external resistor divider that supports the analog levels for 2-, 3-

and 4-MUX operation. Groups of the LCD segment lines can be selected for digital output signals. The

MSP430x32x configuration has four common signal lines and 21 segment lines.

A/D converter

GND. It is a 12+2 bit converter with a software or automatically-controlled range select. Five inputs can be

selected for analog or digital function. A ratiometric current source can be used on four of the analog pins. The

current is adjusted by an external resistor and is enabled/disabled by bits located in the control registers. The

conversion is started by setting the start-of-conversion bit (SOC) in the control register and the

end-of-conversions sets the interrupt flag. The analog input signal is sampled starting with SOC during the next

twelve MCLK clock pulses. The power-down bit in the control register controls the operating mode of the ADC

peripheral. The current consumption and operation is stopped when it is set. The system reset PUC sets the

power-down bit.

Basic Timer1

The Basic Timer1 (BT1) divides the frequency of MCLK or ACLK, as selected with the SSEL bit, to provide low

frequency control signals. This is done within the system by one central divider, the Basic Timer1, to support

low current applications. The BTCTL control register contains the flags which control or select the different

operational functions. When the supply voltage is applied or when a reset of the device (RST/NMI pin), a

watchdog overflow or a watchdog security key violation occurs, and all bits in the register hold undefined or

unchanged status. The user software usually configures the operational conditions on the BT1 during

initialization.

The Basic Timer1 has two 8-Bit timers which can be cascaded to a 16-bit timer. Both timers can be read and

written by software. Two bits in the SFR address range handle the system control interaction according to the

function implemented in the Basic Timer1. These two bits are the Basic Timer1 interrupt flag (BTIFG) and the

Basic Timer1 interrupt enable (BTIE) bit.

Watchdog Timer

The primary function of the Watchdog Timer (WDT) module is to perform a controlled system restart after a

software upset has occurred. If the selected time interval expires, a system reset is generated. If this watchdog

function is not needed in an application, the module can work as an interval timer, which generates an interrupt

after the selected time interval.

The Watchdog Timer counter (WDTCNT) is a 15/16-bit up-counter which is not directly accessible by software.

The WDTCNT is controlled using the Watchdog Timer control register (WDTCTL), which is an 8-Bit read/write

register. Writing to WDTCTL, in both operating modes (watchdog or timer) is only possible by using the correct

password in the high-byte. The low-byte stores data written to the WDTCTL. The high-byte password is 05Ah.

If any value other than 05Ah is written to the high-byte of the WDTCTL, a system reset PUC is generated.

When

the password is read its value is 069h. This minimizes accidental write operations to the WDTCTL register. In

addition to the Watchdog Timer control bits, two bits included in the WDTCTL configure the NMI pin.