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MSP430P337HFD Datasheet(PDF) 7 Page - Texas Instruments |
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MSP430P337HFD Datasheet(HTML) 7 Page - Texas Instruments |
7 / 27 page MSP430x33x MIXED SIGNAL MICROCONTROLLERS SLAS163 – FEBRUARY 1998 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Table 3. Interrupt Functions and Addresses INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY Power-up, external reset, Watchdog WDTIFG Reset 0FFFEh 15, highest NMI, Oscillator fault NMIIFG (see Note 2) OFIFG (see Note 2) non-maskable (non)-maskable 0FFFCh 14 Dedicated I/O P0IFG.0 maskable 0FFFAh 13 Dedicated I/O P0IFG.1 maskable 0FFF8h 12 maskable 0FFF6h 11 Watchdog timer WDTIFG maskable 0FFF4h 10 Timer_A CCIFG0 (see Note 3) maskable 0FFF2h 9 Timer_A TAIFG (see Note 3) maskable 0FFF0h 8 UART Receive URXIFG maskable 0FFEEh 7 UART Transmit UTXIFG maskable 0FFECh 6 0FFEAh 5 Timer/Port See Note 3 maskable 0FFE8h 4 I/O Port P2 P2IFG.07 (see Note 2) maskable 0FFE6h 3 I/O Port P1 P1IFG.07 (see Note 2) maskable 0FFE4h 2 Basic Timer BTIFG maskable 0FFE2h 1 I/O Port P0 P0IFG.27 (see Note 2) maskable 0FFE0h 0, lowest NOTES: 2. Multiple source flags 3. Interrupt flags are located in the module special function registers Most interrupt and module enable bits are collected into the lowest address space. Special function register bits that are not allocated to a functional purpose are not physically present in the device. Simple SW access is provided with this arrangement. interrupt enable 1 and 2 76 5 4 0 P0IE.1 OFIE WDTIE 32 1 P0IE.0 rw-0 rw-0 rw-0 rw-0 Address 0h WDTIE: Watchdog timer interrupt enable signal OFIE: Oscillator fault interrupt enable signal P0IE.0: Dedicated I/O P0.0 interrupt enable signal P0IE.1: P0.1 or 8-bit timer/counter, RXD interrupt enable signal 76 5 4 0 TPIE UTXIE URXIE rw-0 32 1 rw-0 rw-0 rw-0 Address 01h BTIE URXIE: USART receive interrupt enable signal UTXIE: USART transmit interrupt enable signal TPIE: Timer/Port interrupt enable signal BTIE: Basic Timer interrupt enable signal |
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