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MSP430P315DL Datasheet(PDF) 9 Page - Texas Instruments |
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MSP430P315DL Datasheet(HTML) 9 Page - Texas Instruments |
9 / 30 page MSP430x31x MIXED SIGNAL MICROCONTROLLERS SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 special function registers Most interrupt and module enable bits are collected into the lowest address space. Special function register bits that are not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement. interrupt enable 1 and 2 76 5 4 0 P0IE.1 OFIE WDTIE 32 1 P0IE.0 rw-0 rw-0 rw-0 rw-0 Address 0h WDTIE: Watchdog Timer enable signal OFIE: Oscillator fault enable signal P0IE.0: Dedicated I/O P0.0 P0IE.1: P0.1 or 8-Bit Timer/Counter, RXD 76 5 4 0 TPIE rw-0 32 1 rw-0 Address 01h BTIE TPIE: Timer/Port enable signal BTIE: Basic Timer1 enable signal interrupt flag register 1 and 2 76 5 4 0 P0IFG.1 OFIFG WDTIFG 32 1 rw-0 rw-1 rw-0 Address 02h NMIIFG P0IFG.0 rw-0 rw-0 WDTIFG: Set on overflow or security key violation OR Reset on VCC power-on or reset condition at RST/NMI-pin OFIFG: Flag set on oscillator fault P0.0IFG: Dedicated I/O P0.0 P0.1IFG: P0.1 or 8-Bit Timer/Counter, RXD NMIIFG: Signal at RST/NMI-pin 76 5 4 0 rw 32 1 Address 03h BTIFG BTIFG: Basic Timer1 flag module enable register 1 and 2 76 5 4 0 32 1 Address 04h 76 5 4 0 32 1 Address 05h Legend rw: rw-0: Bit can be read and written. Bit can be read and written. It is reset by PUC SFR bit is not present in device. |
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