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SMQ320C50HFG Datasheet(PDF) 1 Page - Texas Instruments |
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SMQ320C50HFG Datasheet(HTML) 1 Page - Texas Instruments |
1 / 31 page SMJ320C50/SMQ320C50 DIGITAL SIGNAL PROCESSOR SGUS020 – JUNE 1996 1 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 D Military Operating Temperature Range: – 55 °C to 125°C D Processed to MIL-PRF-38535 D Fast Instruction Cycle Time (30 ns and 40 ns) D Source-Code Compatible With All ’C1x and ’C2x Devices D RAM-Based Operation – 9K × 16-Bit Single-Cycle On-Chip Program/Data RAM – 1056 × 16-Bit Dual-Access On-Chip Data RAM D 2K × 16-Bit On-Chip Boot ROM D 224K × 16-Bit Maximum Addressable External Memory Space (64K Program, 64K Data, 64K I/O, and 32K Global) D 32-Bit Arithmetic Logic Unit (ALU) – 32-bit Accumulator (ACC) – 32-Bit Accumulator Buffer (ACCB) D 16-Bit Parallel Logic Unit (PLU) D 16 × 16-Bit Multiplier, 32-Bit Product D 11 Context-Switch Registers D Two Buffers for Circular Addressing D Full-Duplex Synchronous Serial Port D Time-Division Multiplexed Serial Port (TDM) D Timer With Control and Counter Registers D 16 Software Programmable Wait-State Generators D Divide-by-One Clock Option D IEEE 1149.1† Boundary Scan Logic D Operations Are Fully Static D Enhanced Performance Implanted CMOS (EPIC ™) 0.72-µm Technology Fabricated by Texas Instruments D Packaging – 141-Pin Ceramic Grid Array (GFA Suffix) – 132-Lead Ceramic Quad Flat Package (HFG Suffix) – 132-Lead Plastic Quad Flat Package (PQ Suffix) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. HFG PACKAGE (TOP VIEW) 99 1 67 33 2 1 3 5 7 9 11 13 15 17 19 V T P M K H F D B W U R N L J G E C A 46 8 10 12 14 16 18 GFA PACKAGE (TOP VIEW) PQ PACKAGE (TOP VIEW) 1 17 18 117 116 50 51 83 84 132 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1996, Texas Instruments Incorporated † IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture EPIC and TI are trademarks of Texas Instruments Incorporated. |
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