SN10KHT5574

OCTAL ECL-TO-TTL TRANSLATOR WITH D-TYPE

EDGE-TRIGGERED FLIP-FLOPS AND 3-STATE OUTPUTS

SDZS010 – JANUARY 1990 – REVISED OCTOBER 1990

Copyright

1

POST OFFICE BOX 655303

Layout

Configurations Minimize High-Speed

Switching Noise

Packages and Standard Plastic DIPs

description

This octal ECL-to-TTL translator is designed to

provide efficient translation between a 10KH ECL

signal environment and a TTL signal environment.

This device is designed specifically to improve the performance and density of ECL-to-TTL CPU/bus-oriented

functions such as memory-address drivers, clock drivers, and bus-oriented receivers and transmitters.

The eight flip-flops of the SN10KHT5574 are edge-triggered D-type flip-flops. On the positive transition of the

clock, the Q outputs are set to the logic levels that were set up at the D inputs.

A buffered output-enable input (OE) can be used to place the eight outputs in either a normal logic state (high

or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive

the bus lines significantly. The high-impedance third state and increased drive provide the capability to drive

bus lines without need for interface or pullup components.

The output-enable input OE does not affect the internal operations of the flip-flops. Old data can be retained

or new data can be entered while the outputs are off.

The SN10KHT5574 is characterized for operation from 0

°C to 75°C.

FUNCTION TABLE

OE

CLK

D

INPUTS

Q

OUTPUT

(TTL)

L

↑

LL

L

↑

HH

LL

X

Qo

HX

X

Z

1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

1Q

2Q

3Q

4Q

GND

GND

GND

5Q

6Q

7Q

8Q

1D

2D

3D

4D

OE(TTL)

GND

CLK(ECL)

5D

6D

7D

8D

DW OR NT PACKAGE

(TOP VIEW)

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.