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EP4SE110 Datasheet(PDF) 8 Page - Altera Corporation |
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EP4SE110 Datasheet(HTML) 8 Page - Altera Corporation |
8 / 40 page Chapter 1: DC and Switching Characteristics 1–6 Electrical Characteristics © December 2008 Altera Corporation Stratix IV Device Handbook, Volume 4 OCT calibration is automatically performed at power-up for OCT-enabled I/Os. Table 1–10 lists OCT variation with temperature and voltage after power-up calibration. Use Equation 1–1 to determine the OCT variation when voltage and temperature vary after power-up calibration. Pin Capacitance Table 1–11 shows the Stratix IV device family pin capacitance. Table 1–9. I/O On-Chip Termination Resistance Tolerance - Preliminary Symbol Description Resistance Tolerance Commercial Unit R OC T_UNCAL Internal series/parallel OCT with calibration ± 5 % R OC T_CAL Internal series/parallel OCT without calibration ± 30 % Equation 1–1. OCT Variation Without Re-Calibration (Note 1) Note to Equation 1–1: (1) R CAL is calibrated on-chip termination at power up. ΔT and ΔV are variations in temperature and voltage with respect to temperature and V CCIO values, respectively, at power up. R OCT R CAL 1 dR dT ------- ΔT dR dV ------- ΔV × + × + ⎝⎠ ⎛⎞ = Table 1–10. On-Chip Termination Variation after Power-Up Calibration - Preliminary Symbol Description V CCIO (V) Commercial Typical Industrial Typical Unit dR/dV OCT variation with voltage without re-calibration 3.0 0.029 — Ω/V 2.5 0.036 — 1.8 0.033 — 1.5 0.033 — 1.2 0.033 — dR/dT OCT variation with temperature without re-calibration 3.0 0.294 — Ω/C 2.5 0.301 — 1.8 0.355 — 1.5 0.344 — 1.2 0.348 — Table 1–11. Stratix IV Device Capacitance (Note 1) - Preliminary (Part 1 of 2) Symbol Description Typical Unit C IOTB Input capacitance on top/bottom I/O pins 8 pF C IOLR Input capacitance on left/right I/O pins 8 pF C CLKTB Input capacitance on top/bottom dedicated clock input pins 5 pF C CLKLR Input capacitance on left/right dedicated clock input pins 5 pF |
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