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EP2SGX60E Datasheet(PDF) 9 Page - Altera Corporation |
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EP2SGX60E Datasheet(HTML) 9 Page - Altera Corporation |
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9 / 314 page  Altera Corporation 2–1 October 2007 2. Stratix II GX Architecture Transceivers Stratix® II GX devices incorporate dedicated embedded circuitry on the right side of the device, which contains up to 20 high-speed 6.375-Gbps serial transceiver channels. Each Stratix II GX transceiver block contains four full-duplex channels and supporting logic to transmit and receive high-speed serial data streams. The transceivers deliver bidirectional point-to-point data transmissions, with up to 51 Gbps (6.375 Gbps per channel) of full-duplex data transmission per transceiver block. Figure 2–1 shows the function blocks that make up a transceiver channel within the Stratix II GX device. Figure 2–1. Stratix II GX Transceiver Block Diagram Notes to Figure 2–1: (1) n represents the number of bits in each word that need to be serialized by the transmitter portion of the PMA or have been deserialized by the receiver portion of the PMA. n = 8, 10, 16, or 20. (2) m represents the number of bits in the word that pass between the FPGA logic and the PCS portion of the transceiver. m = 8, 10, 16, 20, 32, or 40. Transceivers within each block are independent and have their own set of dividers. Therefore, each transceiver can operate at different frequencies. Each block can select from two reference clocks to provide two clock domains that each transceiver can select from. Deserializer Serializer Word Aligner 8B/10B Decoder XAUI Lane Deskew Byte Deserializer 8B/10B Encoder Phase Compensation FIFO Buffer Reference Clock Reference Clock Byte Serializer Phase Compensation FIFO Buffer Rate Matcher PCS Digital Section FPGA Fabric PMA Analog Section Byte Ordering Receiver PLL Transmitter PLL Clock Recovery Unit m n n m (1) (2) (2) (1) SIIGX51003-2.2 |
Similar Part No. - EP2SGX60E |
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Similar Description - EP2SGX60E |
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