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P1145-3SDES Datasheet(PDF) 6 Page - Pletronics, Inc. |
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P1145-3SDES Datasheet(HTML) 6 Page - Pletronics, Inc. |
6 / 7 page P113SD Series 5.0 V CMOS Clock Oscillators July 2007 www.pletronics.com 425-776-1880 6 Mechanical: Inches mm Cover: Kovar Electroless Nickel Plated 1 µinch (25 µm) typical Resistance welded to base Label: White Kapton with Black Letters –or-- Blue Epoxy heat cure ink with laser marked lettering Base: Kovar Glass to metal sealed leads Pin 7 Connected to case Not to scale A 0.787 + _0.005 20.00 + _0.13 B 0.487 + _0.005 12.37 + _0.13 C 0.225 + _0.011 5.72 + _0.28 D 1 0.250 6.35 E 1 0.020 0.51 F 1 0.031 0.79 G 1 0.094 2.37 H 1 0.300 7.62 I 1 0.600 15.24 J 1 0.094 2.37 1 Nominal dimension Pad Function Note 1 Output Enable/Disable When this pad is not connected the oscillator shall operate. When this pad is logic low the output will be inhibited (high impedance state.) Recommend connecting this pad to V CC if the oscillator is to be always on. 7 Ground (GND) 8 Output 14 Supply Voltage (V CC) Recommend connecting appropriate power supply bypass capacitors as close as possible. Layout and application information For Optimum Jitter Performance, Pletronics recommends: • a ground plane under the device • no large transient signals (both current and voltage) should be routed under the device • do not layout near a large magnetic field such as a high frequency switching power supply • do not place near piezoelectric buzzers or mechanical fans. |
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