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SN74ABT8543DW Datasheet(PDF) 9 Page - Texas Instruments |
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SN74ABT8543DW Datasheet(HTML) 9 Page - Texas Instruments |
9 / 25 page SN54ABT8543, SN74ABT8543 SCAN TEST DEVICES WITH OCTAL REGISTERED BUS TRANSCEIVERS SCBS120E – AUGUST 1991 – REVISED JULY 1996 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Table 1. Boundary-Scan Register Configuration BSR BIT NUMBER DEVICE SIGNAL BSR BIT NUMBER DEVICE SIGNAL BSR BIT NUMBER DEVICE SIGNAL BSR BIT NUMBER DEVICE SIGNAL BSR BIT NUMBER DEVICE SIGNAL 39 OEB 31 A8-I 23 A8-O 15 B8-I 7 B8-O 38 OEA 30 A7-I 22 A7-O 14 B7-I 6 B7-O 37 OEAB 29 A6-I 21 A6-O 13 B6-I 5 B6-O 36 OEBA 28 A5-I 20 A5-O 12 B5-I 4 B5-O 35 LEAB 27 A4-I 19 A4-O 11 B4-I 3 B4-O 34 LEBA 26 A3-I 18 A3-O 10 B3-I 2 B3-O 33 CEAB 25 A2-I 17 A2-O 9 B2-I 1 B2-O 32 CEBA 24 A1-I 16 A1-O 8 B1-I 0 B1-O boundary-control register The boundary-control register (BCR) is 11 bits long. The BCR is used in the context of the RUNT instruction to implement additional test operations not included in the basic SCOPE ™ instruction set. Such operations include PRPG, PSA with input masking, and binary count up (COUNT). Table 4 shows the test operations that are decoded by the BCR. During Capture-DR, the contents of the BCR are not changed. At power up or in Test-Logic-Reset, the BCR is reset to the binary value 00000000010, which selects the PSA test operation with no input masking. The BCR order of scan is from TDI through bits 10–0 to TDO. Table 2 shows the BCR bits and their associated test control signals. Table 2. Boundary-Control Register Configuration BCR BIT NUMBER TEST CONTROL SIGNAL BCR BIT NUMBER TEST CONTROL SIGNAL BCR BIT NUMBER TEST CONTROL SIGNAL 10 MASK8 6 MASK4 2 OPCODE2 9 MASK7 5 MASK3 1 OPCODE1 8 MASK6 4 MASK2 0 OPCODE0 7 MASK5 3 MASK1 –– –– bypass register The bypass register is a 1-bit scan path that can be selected to shorten the length of the system scan path, thereby reducing the number of bits per test pattern that must be applied to complete a test operation. During Capture-DR, the bypass register captures a logic 0. The bypass register order of scan is shown in Figure 3. Bit 0 TDO TDI Figure 3. Bypass Register Order of Scan |
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