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ADS-933MC Datasheet(PDF) 3 Page - Murata Power Solutions Inc. |
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ADS-933MC Datasheet(HTML) 3 Page - Murata Power Solutions Inc. |
3 / 8 page ADS-933 ® ® 3 +25°C 0 TO +70°C –55 TO +125°C DYNAMIC PERFORMANCE (Cont.) MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. UNITS ANALOG OUTPUT Overvoltage Recovery Time — — 333 — — 333 — — 333 ns A/D Conversion Rate 3 — — 3 — — 3 — — MHz Internal Reference Voltage 3.15 +3.2 — — +3.2 — — +3.2 — Volts Drift — ±30 — — ±30 — — ±30 — ppm/°C External Current — 5 — — 5 — — 5 — mA DIGITAL OUTPUTS Logic Levels Logic "1" +2.4 — — +2.4 — — +2.4 — — Volts Logic "0" — — +0.4 — — +0.4 — — +0.4 Volts Logic Loading "1" — — –4 — — –4 — — –4 mA Logic Loading "0" — — +4 — — +4 — — +4 mA Output Coding Offset Binary / Complementary Offset Binary / Two's Complement / Complementary Two's Complement POWER REQUIREMENTS Power Supply Ranges } +5V Supply +4.75 +5.0 +5.25 +4.75 +5.0 +5.25 +4.9 +5.0 +5.25 Volts –5V Supply –4.75 –5.0 –5.25 –4.75 –5.0 –5.25 –4.9 –5.0 –5.25 Volts Power Supply Currents +5V Supply — +220 260 — +220 260 — +220 260 mA –5V Supply –140 –150 — –140 –150 — –140 –150 — mA Power Dissipation — 1.85 2.0 — 1.85 2.0 — 1.85 2.0 Watts Power Supply Rejection — — ±0.07 — — ±0.07 — — ±0.07 %FSR/%V Footnotes: Effective bits is equal to: All power supplies must be on before applying a start convert pulse. All supplies and the clock (START CONVERT) must be present during warm-up periods. The device must be continuously converting during this time. When COMP. BITS (pin 35) is low, logic loading "0" will be –350µA. A 3MHz clock with a 50nsec positive pulse width is used for all production testing. See Timing Diagram for more details. 6.02 (SNR + Distortion) – 1.76 + 20 log Full Scale Amplitude Actual Input Amplitude This is the time required before the A/D output data is valid once the analog input is back within the specified range. The minimum supply voltages of +4.9V and –4.9V for ±VDD are required for –55°C operation only. The minimum limits are +4.75V and –4.75V when operating at +125°C. TECHNICAL NOTES 1. Obtaining fully specified performance from the ADS-933 requires careful attention to pc-card layout and power supply decoupling. The device's analog and digital ground systems are connected to each other internally. For optimal performance, tie all ground pins (2, 4, 7, 30 and 36) directly to a large analog ground plane beneath the package. Bypass all power supplies and the +3.2V reference output to ground with 4.7µF tantalum capacitors in parallel with 0.1µF ceramic capacitors. Locate the bypass capacitors as close to the unit as possible. 2. The ADS-933 achieves its specified accuracies without the need for external calibration. If required, the device's small initial offset and gain errors can be reduced to zero using the adjustment circuitry shown in Figure 2. When using this circuitry, or any similar offset and gain calibration hardware, make adjustments following warm-up. To avoid interaction, always adjust offset before gain. Tie pins 5 and 6 to ANALOG GROUND (pin 4) if not using offset and gain adjust circuits. 3. Pin 35 (COMP. BITS) is used to select the digital output coding format of the ADS-933. See Tables 2a and 2b. When this pin has a TTL logic "0" applied, it complements all of the ADS-933’s digital outputs. When pin 35 has a logic "1" applied, the output coding is complementary offset binary. Applying a logic "0" to pin 35 changes the coding to offset binary. Using the MSB output (pin 29) instead of the MSB output (pin 28) changes the respective output codings to complementary two's complement and two's complement. Pin 35 is TTL compatible and can be directly driven with digital logic in applications requiring dynamic control over its function. There is an internal pull-up resistor on pin 35 allowing it to be either connected to +5V or left open when a logic "1" is required. 4. To enable the three-state outputs, connect OUTPUT ENABLE (pin 34) to a logic "0" (low). To disable, connect pin 34 to a logic "1" (high). |
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