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5962-9860801QEA Datasheet(PDF) 2 Page - Texas Instruments |
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5962-9860801QEA Datasheet(HTML) 2 Page - Texas Instruments |
2 / 23 page SN54AHC123A, SN74AHC123A DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS SCLS352H − JULY 1997 − REVISED OCTOBER 2005 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description/ordering information (continued) The output pulse duration is programmed by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistance between Rext/Cext and VCC. The output pulse duration also can be reduced by taking CLR low. Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. The A, B, and CLR inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition rates with jitter-free triggering at the outputs. Once triggered, the basic pulse duration can be extended by retriggering the gated low-level-active (A) or high-level-active (B) input. Pulse duration can be reduced by taking CLR low. CLR input can be used to override A or B inputs. The input/output timing diagram illustrates pulse control by retriggering the inputs and early clearing. The variance in output pulse duration from device to device typically is less than ±0.5% for given external timing components. An example of this distribution for the ’AHC123A is shown in Figure 10. Variations in output pulse duration versus supply voltage and temperature are shown in Figure 6. During power up, Q outputs are in the low state, and Q outputs are in the high state. The outputs are glitch free, without applying a reset pulse. For additional application information on multivibrators, see the application report Designing With the SN74AHC123A and SN74AHCT123A, literature number SCLA014. FUNCTION TABLE (each multivibrator) INPUTS OUTPUTS CLR A B Q Q L X X L H X HX L† H† X XL L† H† H L ↑ H # H ↑ L H † These outputs are based on the assumption that the indicated steady-state conditions at the A and B inputs have been set up long enough to complete any pulse started before the setup. |
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