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FTL-1621-55 Datasheet(PDF) 4 Page - Finisar Corporation. |
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FTL-1621-55 Datasheet(HTML) 4 Page - Finisar Corporation. |
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4 / 9 page  FTL-1621-XX CWDM GBIC Product Specification – February 2007 F i n i s a r © Finisar Corporation February 2007 Rev.B Page 4 IV. High Speed Electrical Interface All high-speed PECL signals are AC coupled internally. Parameter Symbol Min Typ Max Units Notes/Conditions RX_LOS Assert Level -- -42 -39 dBm Measured on Finisar Eval Card RX_LOS Deassert Level -- -37 -32 dBm Measured on Finisar Eval Card RX_LOS Hysteresis -- 1.0 dB Measured on Finisar Eval Card RX_LOS Assert Delay t_loss_on 100 µsec From detection of loss of signal to assertion of RX_LOS RX_LOS Negate Delay t_loss_off 150 µsec From detection of presence of signal to negation of RX_LOS TX_DISABLE Assert Time t_off 1000 µsec Rising edge ot TX_DISABLE to fall of output signal below 10% of nominal TX_DISABLE Negate Time t_on 1000 µsec Falling edge of TX_DISABLE to rise of output signal above 90% of nominal TX_DISABLE Reset Time t_reset 10 µsec TX_DISABLE HIGH before TX_DISABLE set LOW Table 4. Low speed signal parameters Parameter Symbol Min Typ Max Units Notes/Conditions Data Input Voltage Vin 650 2000 mV PECL differential peak - peak Data Output Voltage Vout 370 2000 mV PECL differential peak - peak Duty Cycle -- 50 % PECL rise/fall Tr,Tf 150 psec 20%-80% Differential Bit Error Rate BER 10 -12 PRBS 2 23 - 1 test data pattern Tx Input Impedance Zin 75 ohm Singled ended impedance Rx Output Impedance Zout 75 ohm Singled ended impedance Table 5. High speed electrical interface |
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