4

10 G IGABIT ETHERNET SFP+ 1310 NM

LIMITING TRANSCEI vER, 10 KM REACH

Figure 2

Recommended application schematic for the 10 G SFP+ optical transceiver

Notes

ported. Good impedance matching for the driver and receiver is required.

* Transmission lines should be 100 W differentialtraces.Viasandothertransmissionlinediscontinuitiesshouldbeavoided.InordertomeetthehostTP1outputjitterand

TP4jittertolerancerequirementsitisrecommendedthatthePHYhasbothtransmitterpre-emphasistoequalizethetransmittertracesandreceiverequalizationtoequalizethe

receivertraces.Withappropriatetransmitterpre-emphasisandreceiverequalization,upto8dBoflossat5GHzcanbetolerated.

**R5andR6arerequiredwhenanOpenCollectordriverisusedinplaceofCMOSorTTLdrivers.5kW value is appropriate.

capacitive loading at 100 kHz clock frequency.

Power supply filter component values are provided on page 7.

Receiver (Tx Fault)

Vcc

10 kΩ

CMOS, TTL, or

Open Collector Driver

(Tx Disable)

Open Collector

Bidirectional

SDA

Vcc

Rp***

Vcc

Open Collector

Bidirectional

SCL

Rq

***

Mod_ABS

10 kΩ

Vcc

1 VeeT

2 Tx Fault

3 Tx Disable

4 SDA

5 SCL

6 MOD_ABS

7 RS0

8 LOS

9 RS1

10 VeeR

VeeT 20

TD- 19

TD+ 18

VeeT 17

VccT 16

VccR 15

VeeR 14

RD+ 13

RD- 12

VeeR 11

10 kΩ

Vcc

Receiver (LOS)

R1

R2

L1

L2

Z

PECL Driver

(TX DATA)

C1

C2

C5

C4

C3

CMOS or TTL Driver

(RS0 Rx Rate Select)

CMOS or TTL Driver

(RS1 Tx Rate Select)

Vcc

R6 ∗∗

R5 ∗∗

Vcc

Vcc +3.3V

Input

R3

*

50 Ω

R4

*

50 Ω

PECL Receiver

(RX DATA)

Z

Power Supply Filter

C6

Ry

Rx

Section 2

Application Schematic