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CDK2307BILP64 Datasheet(PDF) 10 Page - Cadeka Microcircuits LLC.

Part # CDK2307BILP64
Description  Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters
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Manufacturer  CADEKA [Cadeka Microcircuits LLC.]
Direct Link  http://www.cadeka.com
Logo CADEKA - Cadeka Microcircuits LLC.

CDK2307BILP64 Datasheet(HTML) 10 Page - Cadeka Microcircuits LLC.

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©2009 CADEKA Microcircuits LLC
www.cadeka.com
10
Data Sheet
Digital and Timing Electrical Characteristics
(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 50 MSPS clock, 50% clock duty cycle,
-1 dBFS input signal, 5pF capacitive load, unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Clock Inputs
Duty Cycle
20
80
% high
Compliance
CMOS, LVDS, LVPECL, Sine Wave
Input Range
Differential input swing
-200
200
mVpp
Differential input swing, sine wave clock input
-800
800
mVpp
Input Common Mode Voltage
Keep voltages within ground and voltage of OVDD
0.3
VOVDD -0.3
V
Input Resistance
Differential
TBD
Input Capacitance
Differential
2
pF
Timing
TPD
Start Up Time Active Mode
From Power Down Mode to Active Mode
900
clk cycles
TSLP
Start Up Time Mode
From Sleep Mode to Active
20
µs
TOVR
Out Of Range Recovery Time
1
clk cycles
TAP
Aperture Delay
0.8
ns
εRMS
Aperture Jitter
<0.5
psrms
TLAT
Pipeline Delay
12
clk cycles
TD
Output Delay (see timing diagram)
5pF load on output bits
3
10
ns
TDC
Output Delay (see timing diagram)
Relative to CLK_EXT
1
6
ns
Logic Inputs
VHI
High Level Input Voltage
VOVDD ≥ 3.0V
2
V
VOVDD = 1.7V – 3.0V
0.8 VOVDD
V
VLI
Low Level Input Voltage
VOVDD ≥ 3.0V
0
0.8
V
VOVDD = 1.7V – 3.0V
0
0.2 VOVDD
V
IHI
High Level Input Leakage Current
-10
10
µA
ILI
Low Level Input Leakage Current
-10
10
µA
CI
Input Capacitance
3
pF
Logic Outputs
VHO
High Level Output Voltage
VOVDD-0.1
V
VLO
Low Level Output Voltage
0.1
V
CL
Max Capacitive Load
Post-driver supply voltage equal to pre-driver
supply voltage VOVDD = VOVDD
5
pF
Post-driver supply voltage above 2.25V (1)
10
pF
Note:
(1) The outputs will be functional with higher loads. However, it is recommended to keep the load on output data bits as low as possible to keep dynamic currents
and resulting switching noise at a minimum.


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