SN54LV126A, SN74LV126A

QUADRUPLE BUS BUFFER GATES

WITH 3-STATE OUTPUTS

SCES131C – MARCH 1998 – REVISED JULY 1998

1

POST OFFICE BOX 655303

CMOS) Process

JESD 17

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

Small-Outline (D, NS), Shrink Small-Outline

(DB), Thin Very Small-Outline (DGV), and

Thin Shrink Small-Outline (PW) Packages,

Ceramic Flat (W) Packages, Chip Carriers

(FK), and DIPs (J)

description

These quadruple bus buffer gates are designed

The ’LV126A devices feature independent line

drivers with 3-state outputs. Each output is

disabled when the associated output-enable (OE)

input is low.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a

pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the

driver.

The SN54LV126A is characterized for operation over the full military temperature range of –55

°C to 125°C. The

SN74LV126A is characterized for operation from –40

°C to 85°C.

FUNCTION TABLE

(each buffer)

INPUTS

OUTPUT

OE

A

Y

H

H

H

H

LL

L

X

Z

Copyright

© 1998, Texas Instruments Incorporated

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1OE

1A

1Y

2OE

2A

2Y

GND

4OE

4A

4Y

3OE

3A

3Y

SN54LV126A ...J OR W PACKAGE

SN74LV126A . . . D, DB, DGV, NS, OR PW PACKAGE

(TOP VIEW)

32 1 20 19

910 11 1213

4

5

6

7

8

18

17

16

15

14

4A

NC

4Y

NC

3OE

1Y

NC

2OE

NC

2A

SN54LV126A . . . FK PACKAGE

(TOP VIEW)

NC – No internal connection

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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.