SN54LVT646, SN74LVT646

3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS

WITH 3-STATE OUTPUTS

SCBS140D – MAY 1992 – REVISED JULY 1995

8

POST OFFICE BOX 655303

timing requirements over recommended operating free-air temperature range (unless otherwise

noted) (see Figure 2)

SN54LVT646

SN74LVT646

VCC = 3.3 V

± 0.3 V

VCC = 2.7 V

VCC = 3.3 V

± 0.3 V

VCC = 2.7 V

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

fclock

Clock frequency

0

150

0

150

0

150

0

150

MHz

tw

Pulse duration, CLK high or low

3.3

3.3

3.3

3.3

ns

t

Setup time, A or B before CLKAB

↑ or

Data high

1.5

1.5

1.3

1.3

ns

tsu

Setu time, A or B before CLKAB

↑ or

CLKBA

↑

Data low

2.5

3.0

2

2.4

ns

th

Hold time, A or B after

CLKAB

↑ or CLKBA↑

0.9

0.9

0.4

0.4

ns

(unless otherwise noted) (see Figure 2)

SN54LVT646

SN74LVT646

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 3.3 V

± 0.3 V

VCC = 2.7 V

VCC = 3.3 V

± 0.3 V

VCC = 2.7 V

UNIT

MIN

MAX

MIN

MAX

MIN

TYP†

MAX

MIN

MAX

fmax

150

150

MHz

tPLH

CLKBA or

AorB

1.2

5.9

6.9

1.8

3.8

5.7

6.7

ns

tPHL

CLKAB

A or B

1.2

5.9

6.6

2.1

3.8

5.7

6.4

ns

tPLH

AorB

BorA

0.8

4.9

5.6

1.3

2.8

4.7

5.4

ns

tPHL

A or B

B or A

0.6

4.8

5.5

1

2.7

4.6

5.3

ns

tPLH

SBA or SAB‡

AorB

1

6.4

7.4

1.4

3.7

6.2

7.2

ns

tPHL

SBA or SAB‡

A or B

1

6.4

7

1.4

3.8

6.2

6.8

ns

tPZH

OE

AorB

0.6

6

7.4

1

3

5.8

7.2

ns

tPZL

OE

A or B

0.6

6.2

7.5

1

3.2

6

7.3

ns

tPHZ

OE

AorB

1.4

6.7

7.1

2.3

4.3

6.5

6.9

ns

tPLZ

OE

A or B

1.4

6.4

6.5

2.2

3.8

5.8

5.9

ns

tPZH

DIR

AorB

0.6

6.7

7.7

1

3.4

6.5

7.5

ns

tPZL

DIR

A or B

0.8

6.5

7.3

1.2

3.4

6.3

7.1

ns

tPHZ

DIR

AorB

0.8

7.4

8.3

1.7

4.1

7.2

8.1

ns

tPLZ

DIR

A or B

1

6.7

7

1.5

3.5

5.8

6.3

ns

† All typical values are at VCC = 3.3 V, TA = 25°C.

‡ These parameters are measured with the internal output state of the storage register opposite to that of the bus input.