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AMIS30585AGA Datasheet(PDF) 5 Page - ON Semiconductor |
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AMIS30585AGA Datasheet(HTML) 5 Page - ON Semiconductor |
5 / 17 page AMIS−30585 http://onsemi.com 5 Figure 3. External Component Connection The goal of the CDREF capacitance is to put the DC voltage of the received signal at the right level for the internal components. See also description of the pin REF_OUT. Table 2. VALUE OF THE RESISTORS AND CAPACITORS C1 560 pF C2 560 pF R1 82 KW R2 39 KW CDREF 1 mF Pin 4: REF_OUT REF_OUT is the analog output pin, which provides the voltage reference used by the A/D converter. This pin must be decoupled from the analog ground by a 1 mF ±10 percent ceramic capacitance (CDREF). This must be done as close as possible on the PCB. See Figure 4. It is not allowed to load this pin with other impedance load. Pin 5: M50HZ_IN M50HZ_IN is the mains frequency analog input pin − 50 or 60 Hz. This pin is used to detect the crossing of the zero voltage on one selected phase. This information is used, after filtering with the internal PLL, to synchronize frames with the mains frequency. In case of direct connection to the mains, the use of a series resistor of 1 MW is advised in order to limit the current flowing through the protection diodes. Pin 6, 19 and 22: IO0, IO1 and IO2 IO0, IO1 and IO2 are general−purpose digital input and output pins. Only the IO2 pin is used – this is an input for the chip. All IOs support 5 V level on the bus (5 V safe IO). When used as outputs, they must be able to deliver the 5 V on the bus if necessary. Outputs are open drain NMOS. The high level is created by opening the internal open drain MOS. The 5 V level is obtained by the use of an external pull−up resistance. Figure 4 gives a representation of a 5 V safe IO. A typical value for the pull−up resistance “RES” is 10 KW. With a larger value for “RES”, the current flowing through this resistance is reduced, hence the switch time from 0 V up to 5 V. IO2 pin is used as T_REQ signal, i.e. the transmission request. So this pin is used as an input pin for the chip in the normal working mode. This signal is used in order to initiate a local communication from the microcontroller to the AMIS−30585. The T_REQ signal is active when low. IO0 and IO1 are assigned to drive external LED. The embedded software defines pin activation. Figure 4. Representation of 5V Safe I/O Pin 7, 8, 9, 10, and 11: TDO, TDI, TCK, TMS, and TRSTB All these pins are part of the JTAG bus interface. It will be connected to the ARM ICE interface box. This provides an access to the embedded ARM processor. These pins are used during the debugging of the embedded software. Pin characteristics are in−line with the ARM JTAG interface specification. They will not be described here. Input pins (TDI, TCK, TMS, and TRSTB) contain internal pull−down resistance. TDO is an output. When not in use, the JTAG interface pins may be left floating. Pin 12: TX_DATA TX_DATA provides the digital output signal not modulated. It gives the logical level associated with the transmitted frequency. So, to transmit a frequency fs, the TX_DATA logical state is 0 and is present on TX_DATA. To transmit a frequency fm, the TX_DATA logical state is 1. This output pin is an open drain. An external pull−up resistance is needed to perform the voltage level associated with a logical one (as for the IOx pins). Pin 13: XIN XIN is the analog input pin of the oscillator. It is connected to the interval oscillator inverter gain stage. The clock signal can be created either internally with the external crystal and two capacitors or by connecting an external clock signal to XIN. For the internal generation case, the two external capacitors and crystal are placed as shown in Figure 5. For the external clock connection, the signal is connected to XIN and XOUT is left unused. |
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