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SN74LVT8996PWR Datasheet(PDF) 1 Page - Texas Instruments |
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SN74LVT8996PWR Datasheet(HTML) 1 Page - Texas Instruments |
1 / 44 page SN54LVT8996, SN74LVT8996 3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS SCBS686A – APRIL 1997 – REVISED DECEMBER 1999 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Members of the Texas Instruments (TI™) Broad Family of Testability Products Supporting IEEE Std 1149.1-1990 (JTAG) Test Access Port (TAP) and Boundary-Scan Architecture D Extend Scan Access From Board Level to Higher Levels of System Integration D Promote Reuse of Lower-Level (Chip/Board) Tests in System Environment D While Powered at 3.3 V, Both the Primary and Secondary TAPs Are Fully 5-V Tolerant for Interfacing to 5-V and/or 3.3-V Masters and Targets D Switch-Based Architecture Allows Direct Connect of Primary TAP to Secondary TAP D Primary TAP Is Multidrop for Minimal Use of Backplane Wiring Channels D Shadow Protocols Can Occur in Any of Test-Logic-Reset, Run-Test/Idle, Pause-DR, and Pause-IR TAP States to Provide for Board-to-Board Test and Built-In Self-Test D Simple Addressing (Shadow) Protocol Is Received/Acknowledged on Primary TAP D 10-Bit Address Space Provides for up to 1021 User-Specified Board Addresses D Bypass (BYP) Pin Forces Primary-to-Secondary Connection Without Use of Shadow Protocols D Connect (CON) Pin Provides Indication of Primary-to-Secondary Connection D High-Drive Outputs (–32-mA IOH, 64-mA IOL) Support Backplane Interface at Primary and High Fanout at Secondary D Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II D ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) D Package Options Include Plastic Small-Outline (DW) and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), and Ceramic DIPs (JT) SN54LVT8996 ...JT PACKAGE SN74LVT8996 . . . DW OR PW PACKAGE (TOP VIEW) A4 A3 A2 A1 A0 BYP GND PTDO PTCK PTMS PTDI PTRST A5 A6 A7 A8 A9 VCC CON STDI STCK STMS STDO STRST 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 17 5 6 7 8 9 10 11 25 24 23 22 21 20 19 43 2 1 28 12 13 14 15 16 A8 A9 VCC NC CON STDI STCK A1 A0 BYP NC GND PTDO PTCK SN54LVT8996 . . . FK PACKAGE (TOP VIEW) 18 27 26 NC – No internal connection description The ’LVT8996 10-bit addressable scan ports (ASP) are members of the Texas Instruments SCOPE ™ testability integrated-circuit family. This family of devices supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit assemblies. Unlike most SCOPE ™ devices, the ASP is not a boundary-scannable device, rather, it applies TI’s addressable-shadow-port technology to the IEEE Std 1149.1-1990 (JTAG) test access port (TAP) to extend scan access beyond the board level. Copyright © 1999, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SCOPE and TI are trademarks of Texas Instruments Incorporated. |
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