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CAT9555WI-T1 Datasheet(PDF) 8 Page - ON Semiconductor |
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CAT9555WI-T1 Datasheet(HTML) 8 Page - ON Semiconductor |
8 / 17 page CAT9555 Doc. No. MD-9003 Rev. I 8 © 2008 SCILLC. All rights reserved Characteristics subject to change without notice INT ¯¯¯: Interrupt Output The open-drain interrupt output is activated when one of the port pins configured as an input changes state (differs from the corresponding input port register bit state). The interrupt is deactivated when the input returns to its previous state or the input port register is read. Since there are two 8-bit ports that are read independently, the interrupt caused by Port 0 will not be cleared by a read of Port 1, or vice versa. Changing an I/O from an output to an input may cause a false interrupt if the state of the pin does not match the contents of the input port register. Figure 4. Simplified Schematic of I/Os Output Port Register Data VCC I/O Pin VSS Input Port Register Data To INT Polarity Register Data Polarity Inversion Register Write Polarity Register Data from Shift Register Read Pulse Write Pulse Write Configuration Pulse Data from Shift Register Data from Shift Register Configuration Register D Q CK Q FF D Q CK Q FF DQ CKQ LATCH DQ CK Q FF Q1 100k Ω Q2 Output Port Register Input Port Register |
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