SN54LVTH373, SN74LVTH373

3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES

WITH 3-STATE OUTPUTS

SCBS689E – MAY 1997 – REVISED APRIL 1999

1

POST OFFICE BOX 655303

Technology (ABT) Design for 3.3-V

Operation and Low Static-Power

Dissipation

Insertion

Need for External Pullup/Pulldown

Resistors

(5-V Input and Output Voltages With

Down to 2.7 V

JESD 17

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

Small-Outline (DW), Shrink Small-Outline

(DB), and Thin Shrink Small-Outline (PW)

Packages, Ceramic Chip Carriers (FK),

Ceramic Flat (W) Package, and Ceramic (J)

DIPs

description

provide a TTL interface to a 5-V system environment.

While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the

Q outputs are latched at the logic levels set up at the D inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high

or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive

the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus

lines without need for interface or pullup components.

OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered

while the outputs are in the high-impedance state.

the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

Copyright

© 1999, Texas Instruments Incorporated

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN54LVTH373 ...J OR W PACKAGE

SN74LVTH373 . . . DB, DW, OR PW PACKAGE

(TOP VIEW)

SN54LVTH373 . . . FK PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

OE

1Q

1D

2D

2Q

3Q

3D

4D

4Q

GND

8Q

8D

7D

7Q

6Q

6D

5D

5Q

LE

3

2 1 20 19

9 10 11 12 13

4

5

6

7

8

18

17

16

15

14

2D

2Q

3Q

3D

4D

8D

7D

7Q

6Q

6D