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SN74ACT3622PCB Datasheet(PDF) 8 Page - Texas Instruments |
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SN74ACT3622PCB Datasheet(HTML) 8 Page - Texas Instruments |
8 / 28 page SN74ACT3622 256 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS247D – AUGUST 1993 – REVISED APRIL 1998 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 FIFO write/read operation (continued) The port-B control signals are identical to those of port A, with the exception that the port-B write/read select (W/RB) is the inverse of the port-A write/read select (W/RA). The state of the port-B data (B0 – B35) outputs is controlled by the port-B chip select (CSB) and the port-B write/read select (W/RB). The B0 – B35 outputs are in the high-impedance state when either CSB is high or W/RB is low. The B0 – B35 outputs are active when CSB is low and W/RB is high. Data is loaded into FIFO2 from the B0 – B35 inputs on a low-to-high transition of CLKB when CSB is low, W/RB is low, ENB is high, MBB is low, and IRB is high. Data is read from FIFO1 to the B0 – B35 outputs by a low-to-high transition of CLKB when CSB is low, W/RB is high, ENB is high, MBB is low, and ORB is high (see Table 3). FIFO reads and writes on port B are independent of any concurrent port-A operation. Table 3. Port-B Enable Function Table CSB W/RB ENB MBB CLKB B0 – B35 OUTPUTS PORT FUNCTION H X X X X In high-impedance state None L L L X X In high-impedance state None L L H L ↑ In high-impedance state FIFO2 write L L H H ↑ In high-impedance state Mail2 write L H L L X Active, FIFO1 output register None L H H L ↑ Active, FIFO1 output register FIFO1 read L H L H X Active, mail1 register None L H H H ↑ Active, mail1 register Mail1 read (set MBF1 high) The setup- and hold-time constraints to the port clocks for the port-chip selects and write/read selects are only for enabling write and read operations and are not related to high-impedance control of the data outputs. If a port enable is low during a clock cycle, the port-chip select and write/read select may change states during the setup- and hold-time window of the cycle. When a FIFO OR flag is low, the next data word is sent to the FIFO output register automatically by the low-to-high transition of the port clock that sets the OR flag high. When the OR flag is high, an available data word is clocked to the FIFO output register only when a FIFO read is selected by the port’s chip select, write/read select, enable, and mailbox select. synchronized FIFO flags Each FIFO is synchronized to its port clock through at least two flip-flop stages. This is done to improve flag-signal reliability by reducing the probability of metastable events when CLKA and CLKB operate asynchronously to one another. ORA, AEA, IRA, and AFA are synchronized to CLKA. ORB, AEB, IRB, and AFB are synchronized to CLKB. Tables 4 and 5 show the relationship of each port flag to FIFO1 and FIFO2. |
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