HCE Series
Miniature amplified pressure sensors
5/11
E / 11652 / A
www.sensortechnics.com
Fig. 2:
3 byte data stream between HCE sensor and master containing the pressure value as a 15 bit information
SPI - SERIAL PERIPHERAL INTERFACE
Fig. 1:
Example of a standard 1 byte SPI data transfer for CPHA=0 and CPOL=0
For further information please refer to
Sensortechnics SPI bus application note
Introduction
The HCE is capable to generate a digital output signal.
The device runs a cyclic program, which will store a corrected
sensor value with 14 bit resolution about every 500 µs within
the output registers of the internal ASIC. This cyclic program
runs independent from the bus communication. In order to
use the pressure sensor for digital signal readout, it should
be connected to a SPI Master device.
SPI specifies four signals: The clock (CLK) is generated by
the master and input to all slaves. MOSI carries data from
master to slave. MISO carries data from slave back to
master. A slave select line (SS) allows individual selection
of a slave device.
SPI Modes
A pair of parameters called clock polarity (CPOL) and clock
phase (CPHA) determine the edges of the clock signal on
which the data are driven and sampled. Each of the two
parameters has two possible states, which allows for four
possible combinations, all of which are incompatible with
one another.
In general the HCE series supports all combinations of
clock phase (CPHA) and polarity (CPOL). By default it is
programmed to CPHA = 0 and CPOL = 0, which means
that data transmission starts with the rising first clock edge
(see Fig 1).
Slave select
The falling edge of the SS line indicates the beginning of
the transfer. Additionally the SS line must not be negated
and reasserted between the three bytes to be transmitted.
Data operation
The MOSI line should always be set to high level. So there
is no data transmission from master to slave. Because of
internal configuration the slave will answer the first byte
with an FFxh. The second and third byte contain the 15 bit
pressure information (see Fig. 2).
Relevant data
Data Byte 2
Data Byte 3
X P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0
X
X
X
X
X
X
X
X
Data Byte 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
MOSI
MISO
SCK cycle
1
2
3
4
5
6
7
8
SCK
(CPOL=0)
MOSI
MISO
SS
MSB
LSB
LSB
MSB
Sampling