SN74FB1653

17BIT LVTTL/BTL UNIVERSAL STORAGE TRANSCEIVER

WITH BUFFERED CLOCK LINE

SCBS702H − AUGUST 1997 − REVISED MARCH 2004

4

POST OFFICE BOX 655303

functional block diagram (continued)

To Seven Other Channels

2OEB

2OEB

2CLKAB

2LEAB

2LEBA

2CLKBA

2OEA

2OEA

2CLKAB

1D

C2

C1

1D

C2

C1

2B2

2AI2

2AO2

2CLK

M

U

X

45

46

43

44

41

42

39

40

14

17

16

62

60

Delay3

M

U

X

2SEL2

63

Delay2

48

2SEL1

Delay1

MUX-MODE DELAY

INPUTS

DELAY PATH†

2SEL1

2SEL2

2CLKAB TO 2CLKAB

2CLKAB TO 2CLK

L

L

No delay

No delay

L

H

No delay

Delay1

H

L

Delay2

Delay1

H

H

Delay3

Delay1

† Refer to delay1 through delay3 in the functional block diagram.