SN74HSTL162822

14-BIT TO 28-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH

SCES091A – DECEMBER 1996 – REVISED APRIL 1997

4

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

th

tsu

LOAD CIRCUIT

Data Input

VREF

1.25 V

0.25 V

VREF

VREF

1.25 V

0.25 V

1.25 V

0.25 V

VREF

tw

Input

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

PULSE DURATION

tPLH

tPHL

VREF

VREF

1.25 V

0.25 V

1.5 V

1.5 V

VOH

VOL

Input

(see Note B)

Output

VREF

From Output

Under Test

CL = 80 pF

(see Note A)

500

Ω

LE

NOTES: A. CL includes probe and jig capacitance.

B. All input pulses are supplied by generators having the following characteristics: PRR

≤ 10 MHz, ZO = 50 Ω, tr ≤ 1 ns, tf ≤ 1 ns.

C. The outputs are measured one at a time with one transition per measurement.

D. tPHL and tPLH are the same as tpd.

Figure 1. Load Circuit and Voltage Waveforms