SN74LVC161284

19BIT BUS INTERFACE

SCAS583J − NOVEMBER 1996 − REVISED FEBRUARY 2005

8

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

Input

(see Note D)

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

S1

VCC × 2 V

Open

GND

500

Ω

500

Ω

Output

Control

Output

Waveform 1

S1 at VCC × 2 V

(see Note C)

Output

Waveform 2

S1 at GND

(see Note C)

VOL

VOH

tPZL

tPZH

tPLZ

tPHZ

1.4 V

1.4 V

3 V

0 V

1.4 V

VOL + 0.3 V

1.4 V

VOH − 0.3 V

0 V

2.7 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

tPLH/tPHL

tPLZ/tPZL

tPHZ/tPZH

Open

VCC × 2 V

GND

TEST

S1

NOTES: A. CL includes probe and jig capacitance.

B. Input rise and fall times are 3 ns.

C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

D. Input rise and fall times are 3 ns. Pulse duration is 150 ns < tw < 10 µs.

E. The outputs are measured one at a time, with one transition per measurement.

tPHL

tPLH

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES (B to A)

2.7 V

VOH

VOL

0 V

1.4 V

50% VCC

Input

(see Note B)

Output

1.4 V

50% VCC

B-TO-A LOAD (Totem Pole)

tPHL

tPLH

From

B or Y Output

Under Test

A-TO-B LOAD OR A-TO-Y LOAD (Totem Pole)

VOLTAGE WAVEFORMS MEASURED AT TP1

PROPAGATION DELAY TIMES (A to B)

2.7 V

VOH

VOL

0 V

500

Ω

CL = 50 pF

(see Note A)

TP1

VCC

CL = 50 pF

(see Note A)

Sink Load

Source Load

1.4 V

VOH − 1.4 V

500

Ω

tPHL

tPLH

Output

1.4 V

VOL + 1.4 V

tw

Figure 2. Load Circuit and Voltage Waveforms