SN74LVC16374

16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP

WITH 3-STATE OUTPUTS

SCAS316B – NOVEMBER 1993 – REVISED JULY 1995

5

POST OFFICE BOX 655303

PARAMETER

TEST CONDITIONS

TYP

UNIT

C d

Power dissipation capacitance per flip flop

Outputs enabled

CL =50 pF f=10MHz

22

pF

Cpd

Power dissipation capacitance per flip-flop

Outputs disabled

CL = 50 pF, f = 10 MHz

9

pF

PARAMETER MEASUREMENT INFORMATION

500

Ω

1.5 V

th

tsu

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT FOR OUTPUTS

S1

6 V

Open

GND

500

Ω

Data Input

Timing Input

1.5 V

2.7 V

0 V

1.5 V

1.5 V

2.7 V

0 V

2.7 V

0 V

1.5 V

1.5 V

tw

Input

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

PULSE DURATION

tPLH

tPHL

tPHL

tPLH

VOH

VOH

VOL

VOL

1.5 V

1.5 V

2.7 V

0 V

1.5 V

1.5 V

Input

1.5 V

Output

Control

Output

Waveform 1

S1 at 6 V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

VOL

VOH

tPZL

tPZH

tPLZ

tPHZ

1.5 V

1.5 V

3 V

0 V

1.5 V

VOL + 0.3 V

1.5 V

VOH – 0.3 V

[ 0 V

2.7 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

Output

Output

tpd

tPLZ/tPZL

tPHZ/tPZH

Open

6 V

GND

TEST

S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR

≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.

D. The outputs are measured one at a time with one transition per measurement.

E. tPLZ and tPHZ are the same as tdis.

F. tPZL and tPZH are the same as ten.

G. tPLH and tPHL are the same as tpd.

Figure 1. Load Circuit and Voltage Waveforms