DB, DW, OR PW PACKAGE

(TOP VIEW)

CLKAB

SAB

DIR

A1

A2

A3

A4

A5

A6

A7

A8

GND

CLKBA

SBA

OE

B1

B2

B3

B4

B5

B6

B7

B8

1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

SN74LVC646

OCTAL BUS TRANSCEIVER AND REGISTER

WITH 3-STATE OUTPUTS

SCAS302A – JANUARY 1993 – REVISED JULY 1995

1

POST OFFICE BOX 655303

CMOS) Submicron Process

Per JEDEC Standard JESD-17

Small-Outline (DW), Shrink Small-Outline

(DB), and Thin Shrink Small-Outline (PW)

Packages

description

The SN74LVC646 consists of bus-transceiver circuits, D-type flip-flops, and control circuitry arranged for

multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus

is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input.

Figure 1 illustrates the four fundamental bus-management functions that can be performed with the

SN74LVC646.

Output-enable (OE) and direction-control (DIR) inputs control the transceiver functions. In the transceiver

mode, data present at the high-impedance port can be stored in either register or in both.

The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. DIR

determines which bus receives data when OE is low. In the isolation mode (OE high), A data can be stored in

one register and B data can be stored in the other register.

When an output function is disabled, the input function is still enabled and can be used to store and transmit

data. Only one of the two buses, A or B, may be driven at a time.

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74LVC646 is characterized for operation from – 40

°C to 85°C.

FUNCTION TABLE

INPUTS

DATA I/Os

OPERATION OR FUNCTION

OE

DIR

CLKAB

CLKBA

SAB

SBA

A1 – A8

B1 – B8

OPERATION OR FUNCTION

X

X

↑

X

X

X

Input

Unspecified†

Store A, B unspecified†

X

XX

↑

X

X

Unspecified†

Input

Store B, A unspecified†

H

X

↑

↑

X

X

Input

Input

Store A and B data

H

X

H or L

H or L

X

X

Input disabled

Input disabled

Isolation, hold storage

L

L

X

X

X

L

Output

Input

Real-time B data to A bus

L

L

X

H or L

X

H

Output

Input

Stored B data to A bus

L

H

X

X

L

X

Input

Output

Real-time A data to B bus

L

H

H or L

X

H

X

Input

Output

Stored A data to B bus

† The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled;

i.e., data at the bus pins is stored on every low-to-high transition of the clock inputs.

Copyright

© 1995, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

EPIC is a trademark of Texas Instruments Incorporated.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.