TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,

TCM129C13A, TC,129C14A, TCM129C16A, TCM129C17A

COMBINED SINGLE-CHIP PCM CODEC AND FILTER

SCTS030E – AUGUST 1989 – REVISED OCTOBER 1996

10

POST OFFICE BOX 655303

receive filter transfer over recommended ranges of supply voltage and operating free-air

temperature (see Figure 2)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

Below 200 Hz

0.15

200 Hz

– 0.5

0.15

300 Hz to 3 kHz

– 0.15

0.15

Gain relative to gain at 1.02 kHz

Input signal at PCM IN is 0 dBm0

3.3 kHz

– 0.35

0.15

dB

3.4 kHz

–1

– 0.1

4 kHz

–14

4.6 kHz

–30

timing requirements

clock timing requirements over recommended ranges of supply voltage and operating free-air temperature

(see Figure 3 and 4)

MIN

NOM

MAX

UNIT

tc(CLK)

Clock period for CLKX, CLKR (2.048-MHz systems)

488

ns

tr, tf

Rise and fall times for CLKX and CLKR

5

30

ns

tw(CLK)

Pulse duration for CLKX and CLKR (see Note 7)

220

ns

tw(DCLK)

Pulse duration, DCLK (fDCLK = 64 Hz to 2.048 MHz) (see Note 7)

220

ns

Clock duty cycle, [tw(CLK)/tc(CLK)] for CLKX and CLKR

45%

50%

55%

NOTE 7: FSX CLK must be phase locked with CLKX. FSR CLK must be phase locked with CLKR.

transmit timing requirements over recommended ranges of supply voltage and operating free-air

temperature, fixed-data-rate mode (see Figure 3)

MIN

MAX

UNIT

td(FSX)

Frame-sync delay time

100

tc(CLK) – 100

ns

tsu(SIGX)

Setup time before bit 7 falling edge of CLKX (TMC29C14A and TCM129C14A only)

0

ns

th(SIGX)

Hold time after bit 8 falling edge of CLKX (TCM29C14A and TCM129C14A only)

0

ns

receive timing requirements over recommended ranges of supply voltages and operating free-air

temperature, fixed-data-rate mode (see Figure 4)

MIN

MAX

UNIT

td(FSR)

Frame-sync delay time

100

tc(CLK)–100

ns

tsu(PCM IN) Receive data setup time

50

ns

th(PCM IN)

Receive data hold time

60

ns

transmit timing requirements over recommended ranges of supply voltage and operating free-air

temperature, variable-data-rate mode (see Figure 5)

MIN

MAX

UNIT

td(TSDX)

Time-slot delay time from DCLKX (see Note 8)

140

td(DCLKX)–140

ns

td(FSX)

Frame sync delay time

100

tc(CLK)–100

ns

tc(DCLKX)

Clock period for DCLKX

488

15620

ns

NOTE 8: tFSLX minimum requirement overrides the td(TSDX) maximum requirement for 64-kHz operation.