TCM29C18, TCM29C19, TCM129C18, TCM129C19

ANALOG INTERFACE FOR DSP

SCTS021D –AUGUST 1987 –REVISED OCTOBER 1996

6

POST OFFICE BOX 655303

receive side (D/A) characteristics (see Note 9)

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

Output offset voltage PWRO + and

PWRO – (single ended)

Relative to ANLG GND

±200

mV

Output resistance at PWRO + and

PWRO –

1

2

Ω

Gain-tracking error with sinusoidal

– 3 dBm0

≥ input level ≥ –40 dBm0,

Ref level = – 10 dBm0

±0.5

dB

g

input (see Notes 5, 6, and 7)

– 40 dBm0 > input level

≥ –50 dBm0,

Ref level = – 10 dBm0

±25

dB

Receive gain tolerance

VI = 1.06 V,

f = 1.02 kHz

1.34

1.69

Vrms

Noise

Ref max output level: 200 Hz to 3 kHz

–70

dB

Supply voltage rejection ratio,

f = 0 Hz to 30-kHz,

Supply signal

200 mV peak to peak

Idle channel,

Narrow band

20

dB

yg

j

,

VCC to VBB (single-ended)

Supply signal = 200 mV peak to peak,

Frequency at PWRO +

Narrow band,

– 20

dB

Crosstalk attenuation, receive to

transmit (single ended)

PCM IN = 0 dB,

Frequency = 1 kHz at PCM OUT

60

dB

Si

l t di t ti

ti

i

id l

0 dBm0

≥ ANLG IN ≥ –30 dBm0

33

Signal-to-distortion ratio, sinusoidal

input (see Note 8)

– 30 dBm0 > ANLG IN

≥ –40 dBm0

27

dB

in ut (see Note 8)

– 40 dBm0 > ANLG IN

≥ –45 dBm0

22

Absolute delay time to PWRO +

Fixed data rate,

fCLKX = 2.048 MHz

190

µs

† All typical values are at VBB = –5 V, VCC = 5 V, and TA = 25°C.

NOTES:

5. Unless otherwise noted, the analog input is a 0-dBm0, 1020-Hz sine wave, where 0 dBm0 is defined as the zero-reference point

of the channel under test. This corresponds to an analog signal input of 1.064 Vrms or an output of 1.503 Vrms.

6. The input amplifier is set for unity gain. The digital input is a PCM bit stream generated by passing a 0-dBm0, 1020-Hz sine wave

through an ideal encoder.

7. The TCM29C18, TCM29C19, TCM129C18, and TCM129C19 are internally connected to set PWRO + and PWRO – to 0 dBM. All

output levels are (sin x)/x corrected.

8. CCITT G.712 – Method 2

9. The receive side (D/A) characteristics are referenced to a 600-

Ω termination.

timing requirements

clock timing requirements over recommended ranges of supply voltage and operating free-air temperature

(see Figures 3 and 4)

MIN

NOM

MAX

UNIT

tc(CLK)

Clock period for CLK (2.048-MHz systems)

488

ns

tr, tf

Rise and fall times for CLK

5

30

ns

tw(CLK)

Pulse duration for CLK

220

ns

tw(DCLK)

Pulse duration, DCLK (fDCLK = 64 kHz to 2.048 MHz)

220

ns

Clock duty cycle, [tw(CLK)/tc(CLK)] for CLK

45%

50%

55%

transmit timing requirements over recommended ranges of supply voltage and operating free-air

temperature, fixed-data-rate mode (see Figure 3)

MIN

MAX

UNIT

td(FSX)

Frame-sync delay time

100

tc(CLK) – 100

ns

receive timing requirements over recommended ranges of supply voltages and operating free-air

temperature, fixed-data-rate mode (see Figure 4)

MIN

MAX

UNIT

td(FSR)

Frame-sync delay time

100

tc(CLK)–100

ns