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TCM29C19DW Datasheet(PDF) 3 Page - Texas Instruments |
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TCM29C19DW Datasheet(HTML) 3 Page - Texas Instruments |
3 / 17 page TCM29C18, TCM29C19, TCM129C18, TCM129C19 ANALOG INTERFACE FOR DSP SCTS021D –AUGUST 1987 –REVISED OCTOBER 1996 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION ANLG IN 14 I Inverting analog input to uncommitted transmit operational amplifier. ANLG GND 13 Analog ground return for all voice circuits. ANLG GND is internally connected to DGTL GND. CLK 9 I Master clock and data clock input for the fixed-data-rate mode. Master (filter) clock only for variable-data-rate mode. CLK is used for both the transmit and receive sections. DCLKR 5 I Fixed-data-rate mode — variable-data-rate mode select. When DCLKR is connected to VBB, the device operates in the fixed-data-rate mode. When DCLKR is not connected to VBB, the device operates in the variable-data-rate mode and DCLKR becomes the receive data clock, which operates at frequencies from 64 kHz to 2.048 MHz. DGTL GND 8 Digital ground for all internal logic circuits. DGTL GND is internally connected to ANLG GND. FSR/TSRE 7 I Frame-synchronization clock input /time-slot enable for the receive channel. In the variable-data-rate mode, this signal must remain high for the duration of the time slot. The receive channel enters the standby state when FSR is TTL low for 30 ms. FSX/TSXE 10 I Frame-synchronization clock input /time-slot enable for transmit channel. FSX/TSXE operates independently of, but in an analogous manner to FSR/TSRE. The transmit channel enters the standby state when FSX is low for 300 ms. GSX 15 O Output terminal of internal uncommitted operational amplifier. Internally, this is the voice signal input to the transmit filter. PCM IN 6 I Receive PCM input. PCM data is clocked in on eight consecutive negative transitions of the receive data clock, which is CLKR in fixed-data-rate timing and DCLKR in variable-data-rate timing. PCM OUT 11 O Transmit PCM output. PCM data is clocked out of pcm out on eight consecutive positive transition of the transmit data clock, which is CLKX in fixed-data-rate timing and DCLKX in variable-data-rate timing. PDN 4 I Power-down select. On the TCM29C18 and the TCM129C18, the device is inactive with a TTL low-level input and active with a TTL high-level input to the terminal. On the TCM29C19 and the TCM129C19, this terminal must be connected to a TTL high level. PWRO + 2 O Noninverting output of power amplifier. PWRO+ can drive transformer hybrids or high-impedance loads directly in either a differential or single-ended configuration. PWRO – 3 O Inverting output of power amplifier. PWRO– is functionally identical to PWRO +. TSX/DCLKX 12 I/O Transmit channel time-slot strobe (output) or data clock (input). In the fixed-data-rate mode, this is an open-drain output to be used as an enable signal for a 3-state buffer. In the variable-data-rate mode, DCLKX becomes the transmit data clock, which operates at TTL levels from 64 kHz to 2.048 MHz. VBB 1 Negative supply voltage. Input is – 5 V ±5%. VCC 16 Positive supply voltage. Input is 5 V ±5%. |
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